AD8363ACPZ-R7 datasheet(24/36 Pages) AD

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AD8363

Rev. 0 | Page 24 of 36

When interfacing with an ADC, use as much of the input

dynamic range as possible to maximize the resolution. It is also

important that the VOUT voltage of the AD8363 does not exceed

the range accepted by the input of the ADC for the power levels

of interest. This must take into account the part-to-part variation of

the AD8363 and its variation over temperature. This is especially

important when the slope is increased. The VOUT distribution

is well characterized at major frequencies bands in the Typical

Performance Characteristics section. Most of the VOUT variation

from part to part and over temperature is due to an intercept

shift; therefore, increasing the slope should not increase the

distribution greatly. When increasing the slope, the intercept

does not change greatly. In Figure 59, the intercept changed

by 0.2 dB after the slope change. Therefore, it is possible to

calculate the maximum voltage for a particular power level

by using the following equation:

NewVMAX = OldVMAX (New Slope/Old Slope)

(20)

For example, Figure 10 shows that the maximum voltage for a

−20 dBm input at 1.9 GHz is 2 V. If the slope is doubled from

52 mV/dB to 104 mV/dB, the maximum voltage at the new

slope is 4 V. The REFIN voltage of the ADC (the voltage that

sets the maximum readable voltage in the ADC) is set to 4.16 V,

assuming a 3 dB margin on its input.

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

–1

–2

–3

–4

–5

–60

–50

–40

–30

–20

–10

–55

–45

–35

–25

–15

–5

PIN (dBm)

100mV SLOPE

50mV SLOPE

ERROR 50mV SLOPE

ERROR 100mV SLOPE

Figure 59. Slope Change from 52 mV/dB to 104 mV/dB, Frequency = 2.14 GHz

OFFSET COMPENSATION/MINIMUM CLPF AND

MAXIMUM CHPF CAPACITANCE VALUES

An offset-nulling loop is used to address small dc offsets within

the internal VGA as shown in Figure 60. The high-pass corner

frequency of this loop is set to about 1 MHz using an on-chip

25 pF capacitor, which is sufficiently low for most RF applications.

The high-pass corner can be lowered further by connecting a

capacitor between CHPF and VPOS.

The input offset voltage varies depending on the actual gain at

which the VGA is operating and, therefore, on the input signal

amplitude. When a large CHPF value is used, the offset correction

process can lag the more rapid changes in the gain of the VGA,

which can increase the time required for the loop to fully settle

for a given steady input amplitude. This can manifest itself in a

jumpy, seemingly oscillatory response of the AD8363.

In measurement mode, take care in choosing CHPF and CLPF

because there is a potential to create oscillations. In general, make

the capacitance on the CLPF pin as large as possible; there is no

maximum on the amount of capacitance that can be added to

this pin. Generally, there is no need for an external capacitor on the

CHPF pin; therefore, the pin can be left open. However, when

trying to get a fast response time and/or when working at low

frequencies, extra care in choosing the proper capacitance values

for CHPF and CLPF is prudent. With the gain control pin (VSET)

connected to VOUT, VSET can slew at a rate determined by the

on-chip squaring cell and CLPF. When VSET is changing with time,

the dc offsets in the VGA also vary with time. The speed at

which VSET slews can create a time varying offset that falls within

the high-pass corner set by CHPF. Therefore, in measurement mode,

take care to set CLPF appropriately to reduce the slew. It is also worth

noting that most of the typical performance data was derived with

CLPF = 3.9 nF and CHPF = 2.7 nF and with a CW waveform.

The minimum appropriate CLPF based on slew rate limitations is

as follows

CLPF > 20 × 10−3/FREQRFIN

(21)

where:

CLPF is in farads.

FREQRFIN is in hertz.

This takes into account the on-chip 25 pF capacitor, CF, in

parallel with CLPF. However, because there are other internal

device time delays that affect loop stability, use a minimum CLPF

of 390 pF.

The minimum appropriate CHPF for a given high-pass pole

frequency is

CHPF = 29.2 × 10−6/FHPPOLE − 25 pF

(22)

where FHPPOLE is in hertz.

The subtraction of 25 pF is a result of the on-chip 25 pF

capacitor in parallel with the external CHPF. Typically, choose

CHPF to give a pole (3 dB corner) at least 1 decade below the

desired signal frequency. Note that the high pass corner of the

offset compensation system is approximately 1 MHz without an

external CHPF; therefore, adding an external capacitor lowers the

corner frequency.

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