AD8363ACPZ-R7 datasheet(25/36 Pages) AD

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AD8363

Rev. 0 | Page 25 of 36

The following example illustrates the proper selection of the input

coupling capacitors, minimum CLPF, and maximum CHPF when

using the AD8363 in measurement mode for a 1 GHz input signal.

Choose the input coupling capacitors that have a 3 dB

corner at least one decade below the input signal frequency.

From Equation 8, C > 10/(2 × π × RFIN × 50) = 32 pF

minimum. According to this calculation, 32 pF is sufficient;

however, the input coupling capacitors should be a much

larger value, typically 0.1 μF. The offset compensation

circuit, which is connected to CHPF, should be the true

determinant of the system high-pass corner frequency and

not the input coupling capactitors. With 0.1 μF coupling

capacitors, signals as low as 32 kHz can couple to the input,

which will be well below the system high-pass frequency.

Choose CLPF to reduce instabilities due to VSET slew rate.

See Equation 21, where FRQRFIN = 1 GHz, and this results in

CLPF > 20 pF. However, as previously mentioned, values below

390 pF are not recommended. For this reason, a 470 pF

capacitor was chosen. In addition, if fast response times are

not required, an even larger CLPF value than given here

should be chosen.

Choose CHPF to set a 3 dB corner to the offset compensation

system. See Equation 22, where FHPPOLE is in this case

100 MHz, one decade below the desired signal. This results

in a negative number and, obviously, a negative value is not

practical. Because the high-pass corner frequency is already

1 MHz, this result simply illustrates that the appropriate

solution is to use no external CHPF capacitor.

It can also be noted that per Equation 9

FreqLP ≈ 1.83 × ITGT/(CLPF)

A CLPF of 470 pF results in a small signal low-pass corner

frequency of approximately 144 kHz. This reflects the bandwidth

of the measurement system, and how fast the user can expect

changes on the output. It does not imply any limitations on the

input RF carrier frequency.

gm2

gm1

A = 1

40dB

g × X2

CHPF

VPOS

VGA

110

Ω

110

Ω

25pF

(INTERNAL)

1pF

IRF

RFIN

Figure 60. Offset Compensation Circuit

CHOOSING A VALUE FOR CLPF

The Small Signal Loop Response section and the Offset

Compensation/Minimum CLPF and Maximum CHPF

Capacitance Values section discussed how to choose the

minimum value capacitance for CLPF based on a minimum

capacitance of 390 pF, slew rate limitation, and frequency of

operation. Using the minimum value for CLPF allows the quickest

response time for pulsed type waveforms (such as WiMAX) but

also allows the most residual ripple on the output caused by the

pseudorandom modulation waveform. There is not a maximum

for the capacitance that can be applied to the CLPF pin, and in

most situations, a large enough capacitor can be added to remove

the residual ripple caused by the modulation and yet allow a fast

enough response to changes in input power.

Figure 61 shows how residual ripple, rise time, and fall time

vary with filter capacitance when the AD8363 is driven by a

single carrier CDMA2000 9CH SR1 signal at 2.14 GHz. The rise

time and fall time is based on a signal that is pulsed between no

signal and 10 dBm but is faster if the input power change is less.

400

350

300

250

200

150

100

2800

2450

2100

1750

1400

1050

700

350

010

100

CLPF CAPACITANCE (nF)

RESIDUAL RIPPLE (mV)

RISE TIME (µs)

FALL TIME (µs)

Figure 61. Residual Ripple, Rise Time, and Fall Time vs. CLPF Capacitance,

Single Carrier CDMA2000 9CH SR1 Signal at 2.14 GHz with 10 dBm Pulse

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