AD8363ACPZ-R7 datasheet(17/36 Pages) AD

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AD8363

By forcing the previo

Rev. 0 | Page 17 of 36

us identity through varying the VGA setpoint,

it is

(5)

Subs

results in

ent device, VSET = VOUT. Solving

for V

= VSLOPE × log10(RMS(RFIN)/VZ)

(7)

V/dB).

trapolated

sing a

o the

tion for more information.)

t Pin

by the

coup

ignal

nput pin should be RF ac-

coupled to common (ground).

apparent that

RMS(VSIG) = √(Mean(VSIG2)) = √(VATG2) = VATG

tituting the value of VSIG from Equation 2

RMS(G0 × RFIN exp(−VSET/VGNS)) = VATG

(6)

When connected as a measurem

OUT

as a function of RFIN

VOU

where:

VSLOPE is 1 V/decade (or 50 m

VZ is the intercept voltage.

When RMS(RFIN) = VZ, because log10(1) = 0, this implies that

VOUT = 0 V, making the intercept the input that forces VOUT = 0

VZ has been fixed to approximately 280 μV (approximately

−58 dBm, referred to 50 Ω) with a CW signal at 100 MHz.

In reality, the AD8363 does not respond to signals less than

~−56 dBm. This means that the intercept is an ex

value outside the operating range of the device.

If desired, the effective value of VSLOPE can be altered by u

resistor divider between VOUT and VSET. (Refer t

Altering the Slope section for more information.)

In most applications, the AGC loop is closed through the

setpoint interface and the VSET pin. In measurement mode,

VOUT is directly connected to VSET. (See the Measurement

Mode Basic Connections section for more information.) In

controller mode, a control voltage is applied to VSET and the

VOUT pin typically drives the control input of an amplification

or attenuation system. In this case, the voltage at the VSET pin

forces a signal amplitude at the RF inputs of the AD8363 th

balances the system through feedback. (See the Controller

Mode Basic Connections sec

RF INPUT INTERFACE

Figure 44 shows the connections of the RF inputs within the

AD8363. The input impedance is set primarily by an internal 50

resistor connected between INHI and INLO. A dc level of

approximately half the supply voltage on each pin is established

internally. Either the INHI pin or the INLO pin can be used as

the single-ended RF input pin. (See the Choice of RF Inpu

section.) If the dc levels at these pins are disturbed,

performance is compromised; therefore, signal coupling

capacitors must be connected from the input signal to INHI

and INLO. The input signal high-pass corner formed

ling capacitors and the internal resistances is

fHIGH-PASS = 1/(2 × π × 50 × C)

(8)

where C is in farads and fHIGH-PASS is in hertz. The input coupling

capacitors must be large enough in value to pass the input s

frequency of interest. The other i

ESD ESD ESD ESD ESD ESD

ESD

ESD ESD ESD ESD ESD ESD

ESD

2.5k

Ω

2.5k

Ω

BIAS

VPOS

INHI

INLO

Figure 44. RF Inputs Simplified Schematic

Extensive ESD protection is employed on the RF inputs, which

363 was designed

lun can be used to

s not necessary, and

a loop to force a squared RF signal

to b

d dc vol

simp

er pole is given by

ITGT/(CLPF)

(9)

ITGT

TGT

; however, ITGT is a squared value of

)

mperature. However, because the RF squaring

ring circuit track with temperature, there is no

temp

e low

seudorandom frequency content that either needs to be

ltered out or sampled and averaged out. See the Choosing a

alue for CLPF section for more information.

limits the maximum possible input amplitude to the AD8363.

CHOICE OF RF INPUT PIN

The dynamic range of the AD8363 can be optimized by choosing

the correct RF input pin for the intended frequency of operation.

Using INHI (Pin 14), users can obtain the best dynamic range at

frequencies up to 2.6 GHz. Above 2.6 GHz, it is recommended

that INLO (Pin 15) be used. At 2.6 GHz, the performance obtained

at the two inputs is approximately equal. The AD8

with a single-ended RF drive in mind. A ba

drive INHI and INLO differentially, but it i

it does not result in improved dynamic range.

SMALL SIGNAL LOOP RESPONSE

The AD8363 uses a VGA in

e equal to a square

tage. This nonlinear loop can be

lified and solved for a small signal loop response. The low-

pass corn

FreqLP ≈ 1.83 ×

where:

ITGT is in amperes.

CLPF is in farads.

FreqLP is in hertz.

is derived from V

VTGT multiplied by a transresistance, namely

ITGT = gm × VTGT2

(10

gm is approximately 18.9 μs, so with VTGT equal to the typically

recommended 1.4 V, ITGT is approximately 37 μA. The value of

this current varies with temperature; therefore, the small signal

pole varies with te

circuit and dc squa

erature variation contribution to the absolute value of VOUT.

For CW signals,

FreqLP ≈ 67.7 × 10−6/(CLPF)

However, signals with large crest factors includ

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