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AD8363ACPZ-R7 数据表(PDF) 21 Page - Analog Devices

部件名 AD8363ACPZ-R7
功能描述  50 Hz to 6 GHz, 50 dB TruPwr??Detector
PDF  36 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD8363ACPZ-R7 数据表(HTML) 21 Page - Analog Devices

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AD8363
Rev. 0 | Page 21 of 36
MEASUREMENT MODE BASIC CONNECTIONS
The AD8363 is placed in measurement mode by connecting
VOUT to VSET. This closes the AGC loop within the device
with VOUT representing the VGA control voltage, which is
required to present the correct rms voltage at the input of the
internal square law detector.
The AD8363 requires a single supply of nominally 5 V. The
supply is connected to the two supply pins, VPOS. Decouple
the pins using two capacitors with values equal or similar to
those shown in Figure 54. These capacitors must provide a low
impedance over the full frequency range of the input, and they
should be placed as close as possible to the VPOS pins. Use two
different capacitor values in parallel to provide a broadband ac
short to ground.
As the input signal is swept over its nominal input dynamic range
of −50 dBm to 0 dBm, the output swings from approximately 0 V
to a high value of approximately 3 V.
Input signals can be applied differentially or single-ended; however,
in both cases, the input impedance is 50 Ω. Most performance
information in this data sheet was derived with a single-ended
drive. The optimal measurement range is achieved using a single-
ended drive on the INHI pin at frequencies below 2.6 GHz (as
shown in Figure 54), and likewise, optimal performance is achieved
using the INLO pin above 2.6 GHz (similar to Figure 54; except
INLO is ac-coupled to the input and INHI is ac-coupled to ground).
TEMP
8
7
6
5
VOUT
TCM1
13
14
15
16
VREF
VPOS2
12
11
10
9
12
3
4
TCM2/PWDN
VPOS1
NC
INHI
INLO
TCM1
TEMP
VSET
VOUT
CLPF
AD8363
DUT1
C12
0.1µF
C10
0.1µF
C7
0.1µF
C5
100pF
LOW FREQUENCY INPUT
C9
0.1µF
C4
100pF
C13
0.1µF
C3
OPEN
PADDLE
AGND
R11
1.4k
Ω
R10
845
Ω
Figure 54. Measurement Mode Basic Connections



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