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AD8363

Rev. 0 | Page 23 of 36

Increasing the amount of calibration points can increase the

accuracy of the room temperature performance over a select

power level. Figure 56 shows the same measured data as Figure 55;

except that one calibration point was added at −7 dBm giving

an increase in room temperature linearity between −20 dBm to

+4 dBm. Figure 56 is similar to Figure 14, except Figure 14 includes

more parts and assumes many more calibration points, specifically

1 dB steps from −20 dBm to −40 dBm.

Even though a large amount of calibration points is less practical,

Figure 14 is helpful because it shows the true temperature

performance no matter the location of the calibration point. As

can be seen from both Figure 14 and Figure 56, the temperature

performance tends to change at power levels above −15 dBm.

As shown in Figure 14, because the distribution of temperature

performance is tight for the higher power levels, VTCM1 and

VTCM2 can be optimized for the higher power levels, or a separate

offset can be placed in the calibration routine that adds offsets for

changes in temperature.

Figure 57 shows a two-point calibration like Figure 55 but the

calibration points were changed from −40 dBm and −21 dBm

to −39 dBm and −11 dBm. This demonstrates how calibration

points can be adjusted to increase dynamic range at the expense

of linearity. The higher power calibration point was moved to a

point where the AD8363 is not as linear. At 25°C, there is an error

of 0 dB at the calibration points. Note that the range over which

the AD8363 maintains an error of <±0.5 dB is extended to +53 dB

at 25°C. The disadvantage of this approach is that linearity suffers

and the linearity at −25 dBm degrades by about 0.2 dB and the

error at +3 dBm increases by about 0.7 dB.

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

2.5

1.5

0.5

–0.5

–1.5

–2.5

–60

–50

–40

–30

–20

–10

PIN, INHI (dBm)

+25°C

–40°C

+85°C

Figure 57. 2.14 GHz Transfer Function with Change in

Two-Point Calibration Points

ALTERING THE SLOPE

None of the changes to operating conditions discussed so far

effect the AD8363 logarithmic slope. The slope of the AD8363

can be easily increased or decreased. To reduce the slope, add a

voltage divider on the output, VOUT. To increase the slope, control

the fraction of VOUT that is fed back to the setpoint interface at

the VSET pin. When the full signal from VOUT is applied to

VSET, the slope assumes its nominal value of 52 mV/dB. It can

be increased by including a voltage divider between these pins,

as shown in Figure 58.

TEMP

VSET

VOUT

CLPF

Figure 58. Altering the Slope

Use moderately low resistance values to minimize the scaling

errors from the approximately 72 kΩ input resistance at the

VSET pin. Note that this resistor string also loads the output,

and eventually, it reduces the load driving capabilities, if very

low values are used. Equation 19 can be used to calculate the

resistor values.

R1 = R2' (SD/52 − 1)

(19)

where:

SD is the desired slope, expressed in mV/dB.

R2' is the value of R2 in parallel with 72 kΩ.

The typical slope of the AD8363 is 52; adjust this as needed.

Figure 59 shows a comparison between the regular slope of a

part and when the slope is doubled. For this example, R1 =

1.65 kΩ and R2 = 1.69 kΩ (R2' = 1.65 kΩ). The initial slope

was 52 mV/dB, and it increased to 104 mV/dB. The choice of

100 mV/dB scaling is useful when the output is applied to a

digital voltmeter because the displayed number directly reads

as a decibel quantity with only a decimal point shift.

When measuring a particular section of the input range,

operating at a high slope is useful. With a slope of 104 mV/dB,

a measurement range of 50 dB corresponds to a 5.2 V change in

VOUT, exceeding the capacity of the output stage of the AD8363,

when operating on a 5 V supply. Figure 59 clearly shows this effect.

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