ADCLK846

Rev. A | Page 7 of 16

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

1

2

CLK

3

CLK

4

5

CTRL_A

6

CTRL_B

15 OUT3 (OUT3A)

17 OUT2 (OUT2B)

18 OUT2 (OUT2A)

14 OUT3 (OUT3B)

ADCLK846

TOP VIEW

(Not to Scale)

NOTES:

1. EXPOSED PADDLE MUST BE CONNECTED TO GND.

Figure 2. Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

Reference Voltage.

2

CLK

Clock Input (Negative).

3

CLK

Clock Input (Positive).

4, 10, 13, 16, 19, 22

Supply Voltage.

5

CTRL_A

CMOS Input Control for Output 1 to Output 0. (0: LVDS, 1: CMOS.)

6

CTRL_B

CMOS Input Control for Output 5 to Output 2. (0: LVDS, 1: CMOS.)

7

SLEEP

CMOS Input for Sleep Mode. (0: normal operation, 1: sleep.)

8

OUT5 (OUT5B)

Complementary Side of Differential LVDS Output 5, or CMOS Output 5 on Channel B.

9

OUT5 (OUT5A)

True Side of Differential LVDS Output 5, or CMOS Output 5 on Channel A.

11

OUT4 (OUT4B)

Complementary Side of Differential LVDS Output 4, or CMOS Output 4 on Channel B.

12

OUT4 (OUT4A)

True Side of Differential LVDS Output 4, or CMOS Output 4 on Channel A.

14

OUT3 (OUT3B)

Complementary Side of Differential LVDS Output 3, or CMOS Output 3 on Channel B.

15

OUT3 (OUT3A)

True Side of Differential LVDS Output 3, or CMOS Output 3 on Channel A.

17

OUT2 (OUT2B)

Complementary Side of Differential LVDS Output 2, or CMOS Output 2 on Channel B.

18

OUT2 (OUT2A)

True Side of Differential LVDS Output 2, or CMOS Output 2 on Channel A.

20

OUT1 (OUT1B)

Complementary Side of Differential LVDS Output 1, or CMOS Output 1 on Channel B.

21

OUT1 (OUT1A)

True Side of Differential LVDS Output 1, or CMOS Output 1 on Channel A.

23

OUT0 (OUT0B)

Complementary Side of Differential LVDS Output 0, or CMOS Output 0 on Channel B.

24

OUT0 (OUT0A)

True Side of Differential LVDS Output 0, or CMOS Output 0 on Channel A.

(25)

EPAD

Exposed Paddle. The exposed paddle must be connected to ground.