ADCLK846

Rev. A | Page 13 of 16

APPLICATIONS INFORMATION

USING THE ADCLK846 OUTPUTS FOR ADC CLOCK

APPLICATIONS

Any high speed analog-to-digital converter (ADC) is extremely

sensitive to the quality of the sampling clock provided by the

user. An ADC can be thought of as a sampling mixer, and any

noise, distortion, or timing jitter on the clock is combined with

the desired signal at the ADC output. Clock integrity require-

ments scale with the analog input frequency and resolution,

with higher analog input frequency applications at ≥14-bit

resolution being the most stringent. The theoretical SNR of

an ADC is limited by the ADC resolution and the jitter on

the sampling clock. Considering an ideal ADC of infinite

resolution where the step size and quantization error can be

ignored, the available SNR can be expressed approximately by

⎥

⎥

⎦

⎤

⎢

⎢

⎣

⎡

=

J

f

SNR

2π

1

20log

where:

Figure 24 shows the required sampling clock jitter as a function

of the analog frequency and effective number of bits (ENOB).

See AN-756 Application Note and AN-501 Application Note

for more information.

10

1k

100

30

40

50

60

70

80

90

100

110

6

8

10

12

14

16

18

T

J

S

S

S

1ps

2ps

10ps

SNR = 20log

1

Figure 24. SNR and ENOB vs. Analog Input Frequency

Many high performance ADCs feature differential clock inputs

to simplify the task of providing the required low jitter clock on

a noisy PCB. Distributing a single-ended clock on a noisy PCB

can result in coupled noise on the sample clock. Differential

distribution has inherent common-mode rejection that can

provide superior clock performance in a noisy environment.

The ADCLK846 features LVDS outputs that provide differential

clock outputs, which enable clock solutions that maximize con-

verter SNR performance. Consider the input requirements of

the ADC (differential or single-ended, logic level, termination)

when selecting the best clocking/converter solution.

LVDS CLOCK DISTRIBUTION

The ADCLK846 provides clock outputs that are selectable

as either CMOS or LVDS level outputs. LVDS is a differential

output option that uses a current-mode output stage. The

nominal current is 3.5 mA, which yields 350 mV output swing

across a 100 Ω resistor. The LVDS output meets or exceeds all

ANSI/TIA/EIA-644 specifications. A recommended termina-

tion circuit for the LVDS outputs is shown in Figure 25.

If ac coupling is necessary, place decoupling capacitors either

before or after the 100 Ω termination resistor.

LVDS

100Ω

DIFFERENTIAL (COUPLED)

LVDS

100Ω

Figure 25. LVDS Output Termination

See the AN-586 Application Note at www.analog.com for more

information on LVDS.

CMOS CLOCK DISTRIBUTION

The output drivers of the ADCLK846 can also be configured

as CMOS drivers. When selected as a CMOS driver, each

output becomes a pair of CMOS outputs. These outputs are

1.8 V CMOS compatible.

When single-ended CMOS clocking is used, some of the

following guidelines outlined in this section apply.

Design point-to-point connections such that each driver has

only one receiver, if possible. Connecting outputs in this manner

allows for simple termination schemes and minimizes ringing

due to possible mismatched impedances on the output trace.

Series termination at the source is generally required to provide

transmission line matching and/or to reduce current transients

at the driver.

The value of the resistor is dependent on the board design and

timing requirements (typically 10 Ω to 100 Ω is used). CMOS

outputs are also limited in terms of the capacitive load or trace

length that they can drive. Typically, trace lengths less than

3 inches are recommended to preserve signal rise/fall times

and signal integrity.

CMOS

CMOS

10Ω

60.4Ω

(1.0 INCH)

MICROSTRIP

Figure 26. Series Termination of CMOS Output