ADCLK846SLASHPCBZ datasheet(1/16 Pages) AD

部件名	ADCLK846/PCBZ

功能描述	1.8 V, 6 LVDS/12 CMOS Outputs Low Power Clock Fanout Buffer

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制造商	AD [Analog Devices]

网页	http://www.analog.com

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1.8 V, 6 LVDS/12 CMOS Outputs

Low Power Clock Fanout Buffer

ADCLK846

Rev. A

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rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No

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Tel: 781.329.4700

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Fax: 781.461.3113

FEATURES

Selectable LVDS/CMOS outputs

Up to 6 LVDS (1.2 GHz) or 12 CMOS (250 MHz) outputs

<16 mW per channel (100 MHz operation)

54 fs integrated jitter (12 kHz to 20 MHz)

100 fs additive broadband jitter

2.0 ns propagation delay (LVDS)

135 ps output rise/fall (LVDS)

65 ps output-to-output skew (LVDS)

Sleep mode

Pin-programmable control

1.8 V power supply

APPLICATIONS

Low jitter clock distribution

Clock and data signal restoration

Level translation

Wireless communications

Wired communications

Medical and industrial imaging

ATE and high performance instrumentation

FUNCTIONAL BLOCK DIAGRAM

OUT0 (OUT0A)

OUT0 (OUT0B)

OUT1 (OUT1A)

OUT1 (OUT1B)

OUT2 (OUT2A)

OUT2 (OUT2B)

OUT3 (OUT3A)

OUT3 (OUT3B)

OUT4 (OUT4A)

OUT4 (OUT4B)

OUT5 (OUT5A)

OUT5 (OUT5B)

LVDS/CMOS

CLK

CTRL_A

CTRL_B

SLEEP

VREF

CLK

ADCLK846

Figure 1.

GENERAL DESCRIPTION

The ADCLK846 is a 1.2 GHz/250 MHz, LVDS/CMOS, fanout

buffer optimized for low jitter and low power operation. Possible

configurations range from 6 LVDS to 12 CMOS outputs,

including combinations of LVDS and CMOS outputs. Two

control lines are used to determine whether fixed blocks of

outputs are LVDS or CMOS outputs.

The clock input accepts various types of single-ended and

differential logic levels including LVPECL, LVDS, HSTL, CML,

and CMOS.

Table 8 provides interface options for each type of connection.

The SLEEP pin enables a sleep mode to power down the device.

This device is available in a 24-pin LFCSP package. It is specified

for operation over the standard industrial temperature range of

−40°C to +85°C.

类似零件编号 - ADCLK846/PCBZ

制造商	部件名	数据表	功能描述
Analog Devices	ADCLK846	390Kb / 3P	Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers REV. A
	ADCLK846	468Kb / 15P	1.8 V, 6 LVDS/12 CMOS Outputs Low Power Clock Fanout Buffer 9/2017-Rev. B to Rev. C
	ADCLK846BCPZ	468Kb / 15P	1.8 V, 6 LVDS/12 CMOS Outputs Low Power Clock Fanout Buffer 9/2017-Rev. B to Rev. C
	ADCLK846BCPZ-REEL7	468Kb / 15P	1.8 V, 6 LVDS/12 CMOS Outputs Low Power Clock Fanout Buffer 9/2017-Rev. B to Rev. C
	ADCLK846	468Kb / 15P	1.8 V, 6 LVDS/12 CMOS Outputs Low Power Clock Fanout Buffer 9/2017-Rev. B to Rev. C

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类似说明 - ADCLK846/PCBZ

制造商	部件名	数据表	功能描述
Motorola, Inc	MC100ES7111	129Kb / 8P	LOW VOLTAGE 1:10 DIFFERENTIAL LVDS CLOCK FANOUT BUFFER
Analog Devices	ADCLK854	548Kb / 16P	1.8 V, 12-LVDS/24-CMOS Output, Low Power Clock Fanout Buffer REV. 0
Integrated Device Techn...	MC100ES8014	496Kb / 7P	Low Voltage 1:5 Differential LVDS Clock Fanout Buffer
ON Semiconductor	NB3N853501E	223Kb / 9P	Differential Clock Fanout Buffer Outputs November, 2011 ??Rev. 2
Integrated Device Techn...	8SLVD1212	555Kb / 21P	1:12, LVDS Output Fanout Buffer
	8T74S208C-01	469Kb / 20P	2.5 V Differential LVDS Clock Divider and Fanout Buffer
	8SLVD1212	500Kb / 20P	1:12, LVDS Output Fanout Buffer
Analog Devices	ADCLK846	468Kb / 15P	1.8 V, 6 LVDS/12 CMOS Outputs Low Power Clock Fanout Buffer 9/2017-Rev. B to Rev. C
Diodes Incorporated	PI6C5921512	1Mb / 14P	12 Output LVDS Fanout Buffer Rev 1-2
Renesas Technology Corp	8T74S208C-01	666Kb / 21P	2.5 V Differential LVDS Clock Divider and Fanout Buffer August 22, 2016