| 数据搜索系统,热门电子元器件搜索 |
|
ADCLK846/PCBZ 数据表(PDF) 12 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
ADCLK846/PCBZ 数据表(HTML) 12 Page - Analog Devices |
|
12 / 16 page ![]() ADCLK846 Rev. A | Page 12 of 16 CLOCK OUTPUTS Each driver consists of a differential LVDS output or two single- ended CMOS outputs (always in phase). When the LVDS driver is enabled, the corresponding CMOS driver is in tristate. When the CMOS driver is enabled, the corresponding LVDS driver is powered down and tristated. Figure 21 and Figure 22 display the equivalent output stage. OUTx OUTx 3.5mA VS 3.5mA Figure 21. LVDS Output Simplified Equivalent Circuit OUTxA VS OUTxB VS Figure 22. CMOS Equivalent Output Circuit CONTROL AND FUNCTION PINS Logic Select for CTRL_A CTRL_A selects either CMOS (high) or LVDS (low) logic for Output 1 and Output 0. This pin has an internal 200 kΩ pull- down resistor. Logic Select for CTRL_B CTRL_B selects either CMOS (high) or LVDS (low) logic for Output 5, Output 4, Output 3, and Output 2. This pin has an internal 200 kΩ pull-down resistor. Sleep Mode SLEEP powers down the chip except for the band gap. The input is active high, which puts the outputs into a high-Z state. This pin has a 200 kΩ pull-down resistor. The control pins are operational during sleep mode. POWER SUPPLY The ADCLK846 requires a 1.8 V ± 5% power supply for VS. Best practice recommends bypassing the power supply on the PCB with adequate capacitance (>10 μF) and bypassing all power pins with adequate capacitance (0.1 μF) as close to the part as possible. The layout of the ADCLK846 evaluation board (ADCLK846/PCBZ) provides a good layout example. Exposed Metal Paddle The exposed metal paddle on the ADCLK846 package is an electrical connection, as well as a thermal enhancement. For the device to function properly, the paddle must be properly attached to ground (GND). The ADCLK846 dissipates heat through its exposed paddle. The PCB acts as a heat sink for the ADCLK846. The PCB attachment must provide a good thermal path to a larger heat dissipation area, such as the ground plane on the PCB. This requires a grid of vias from the top layer down to the ground plane. See Figure 23 for an example. VIAS TO GND PLANE Figure 23. PCB Land Example for Attaching Exposed Paddle |
|
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |