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ADCLK854/PCBZ 数据表(PDF) 4 Page - Analog Devices |
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ADCLK854/PCBZ 数据表(HTML) 4 Page - Analog Devices |
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4 / 16 page  ADCLK854 Rev. 0 | Page 4 of 16 TIMING CHARACTERISTICS Table 2. Timing Characteristics Parameter Symbol Min Typ Max Unit Conditions LVDS OUTPUTS Termination = 100 Ω differential; 3.5 mA Output Rise/Fall Time tR , tF 135 235 ps 20% to 80% measured differentially Propagation Delay, Clock-to-LVDS Output tPD 1.5 2.0 2.7 ns VICM = VREF, VID = 0.5 V Temperature Coefficient 2.0 ps/°C Output Skew1 LVDS Outputs in the Same Bank 50 ps All LVDS Outputs On the Same Part 65 ps Across Multiple Parts 390 ps Additive Time Jitter Integrated Random Jitter 54 fs rms BW = 12 kHz to 20 MHz; clock = 1000 MHz 74 fs rms BW = 50 kHz to 80 MHz; clock = 1000 MHz 86 fs rms BW = 10Hz to 100 MHz; clock = 1000 MHz Broadband Random Jitter 2 150 fs rms Input slew = 1 V/ns, see Figure 11 Crosstalk Induced Jitter 260 fs rms Calculated from spur energy with an interferer 10 MHz offset from the carrier CMOS OUTPUTS Output Rise/Fall Time tR, tF 525 950 ps 20% to 80%; CLOAD = 10 pF Propagation Delay, Clock-to-CMOS Output tPD 2.5 3.2 4.2 ns 10 pF load Temperature Coefficient 2.2 ps/°C Output Skew1 CMOS Outputs in the Same Bank 155 ps All CMOS Outputs On the Same Part 175 ps Across Multiple Parts 640 ps Additive Time Jitter Integrated Random Jitter 56 fs rms BW = 12 kHz to 20 MHz; clock = 200 MHz Broadband Random Jitter2 100 fs rms Input slew = 2 V/ns, see Figure 11 Crosstalk Induced Jitter 260 fs rms Calculated from spur energy with an interferer 10 MHz offset from the carrier LVDS-TO-CMOS OUTPUT SKEW 3 LVDS Output(s) and CMOS Output(s) on the Same Part 0.8 1.6 ns CMOS load = 10 pF and LVDS load = 100 Ω 1 This is the difference between any two similar delay paths while operating at the same voltage and temperature. 2 Calculated from the SNR of the ADC method. 3 Measured at the rising edge of the clock signal. |
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