ADCLK854SLASHPCBZ datasheet(5/16 Pages) AD

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ADCLK854

Rev. 0 | Page 5 of 16

CLOCK CHARACTERISTICS

Table 3. Clock Output Phase Noise

Parameter

Min

Typ

Max

Unit

Conditions

CLOCK-TO-LVDS ABSOLUTE PHASE NOISE

Input slew rate > 1 V/ns

1000 MHz

−90

dBc/Hz

@ 10 Hz offset

−108

dBc/Hz

@ 100 Hz offset

−117

dBc/Hz

@ 1 kHz offset

−126

dBc/Hz

@ 10 kHz offset

−135

dBc/Hz

@ 100 kHz offset

−141

dBc/Hz

@ 1 MHz offset

−146

dBc/Hz

@ 10 MHz offset

CLOCK-TO-CMOS ABSOLUTE PHASE NOISE

Input slew rate > 1 V/ns

200 MHz

−101

dBc/Hz

@ 10 Hz offset

−119

dBc/Hz

@ 100 Hz offset

−127

dBc/Hz

@ 1 kHz offset

−138

dBc/Hz

@ 10 kHz offset

−147

dBc/Hz

@ 100 kHz offset

−153

dBc/Hz

@ 1 MHz offset

−156

dBc/Hz

@ 10 MHz offset

LOGIC AND POWER CHARACTERISTICS

Table 4. Control Pin Characteristics

Parameter

Symbol

Min

Typ

Max

Unit

Conditions

CONTROL PINS (IN_SEL, CTRL_x, SLEEP) 1

Logic 1 Voltage

VIH

VS − 0.4

Logic 0 Voltage

VIL

0.4

Logic 1 Current

IIH

μA

Logic 0 Current

IIL

−5

μA

Capacitance

POWER

Supply Voltage Requirement

1.71

1.8

1.89

VS = 1.8 V ± 5%

LVDS Outputs

Full operation

LVDS @ 100 MHz

100

All outputs enabled as LVDS and loaded, RL = 100 Ω

LVDS @ 1200 MHz

175

215

All outputs enabled as LVDS and loaded, RL = 100 Ω

CMOS Outputs

Full operation

CMOS @ 100 MHz

115

140

All outputs enabled as CMOS and loaded, CL = 10 pF

CMOS @ 250 MHz

265

325

All outputs enabled as CMOS and loaded, CL = 10 pF

SLEEP

SLEEP pin pulled high; does not include power dissipated

in the external resistors

Power Supply Rejection 2

LVDS

PSR

0.9

ps/mV

CMOS

PSR

1.2

ps/mV

1 These pins each have a 200 kΩ internal pull-down resistor.

2 Change in tPD per change in VS.

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