ADCLK854

Rev. 0 | Page 14 of 16

APPLICATIONS INFORMATION

USING THE ADCLK854 OUTPUTS FOR ADC CLOCK

APPLICATIONS

Any high speed, analog-to-digital converter (ADC) is extremely

sensitive to the quality of the sampling clock provided by the

user. An ADC can be thought of as a sampling mixer, and any

noise, distortion, or timing jitter on the clock is combined with

the desired signal at the analog-to-digital output. Clock integrity

requirements scale with the analog input frequency and resolu-

tion, with higher analog input frequency applications at ≥14-bit

resolution being the most stringent. The theoretical SNR of an

ADC is limited by the ADC resolution and the jitter on the

sampling clock. Considering an ideal ADC of infinite resolution

where the step size and quantization error can be ignored, the

available SNR can be expressed approximately by

⎥

⎥

⎦

⎤

⎢

⎢

⎣

⎡

×

=

J

f

SNR

2π

1

log

20

is the rms jitter on the sampling clock.

Figure 24 shows the required sampling clock jitter as a function

of the analog frequency and effective number of bits (ENOB).

For more information, see Application Note AN-756 and

Application Note AN-501 at www.analog.com.

10

1k

100

30

40

50

60

70

80

90

100

110

6

8

10

12

14

16

18

T

J

S

S

S

1ps

2ps

10ps

SNR = 20log

1

Figure 24. SNR and ENOB vs. Analog Input Frequency

Many high performance ADCs feature differential clock inputs

to simplify the task of providing the required low jitter clock on

a noisy PCB. Distributing a single-ended clock on a noisy PCB

can result in coupled noise on the sample clock. Differential

distribution has inherent common-mode rejection that can

provide superior clock performance in a noisy environment.

Consider the input requirements of the ADC (differential or

single-ended, logic level, and termination) when selecting the

best clocking/converter solution.

LVDS CLOCK DISTRIBUTION

The ADCLK854 provides clock outputs that are selectable as

either CMOS or LVDS level outputs. LVDS is a differential

output option that uses a current-mode output stage. The

nominal current is 3.5 mA, which yields 350 mV output swing

across a 100 Ω resistor. The LVDS output meets or exceeds all

ANSI/TIA/EIA-644 specifications. A recommended termination

circuit for the LVDS outputs is shown in Figure 25.

If ac coupling is necessary, place decoupling capacitors either before

or after the 100 Ω termination resistor. See Application Note

AN-586 at www.analog.com for more information on LVDS.

LVDS

100Ω

DIFFERENTIAL (COUPLED)

LVDS

100Ω

Figure 25. LVDS Output Termination

CMOS CLOCK DISTRIBUTION

The output drivers of the ADCLK854 can be configured as

CMOS drivers. When selected as a CMOS driver, each output

becomes a pair of CMOS outputs. These outputs are 1.8 V

CMOS compatible.

When single-ended CMOS clocking is used, some of the

following guidelines apply.

Design point-to-point connections such that each driver has only

one receiver, if possible. Connecting outputs in this manner allows

for simple termination schemes and minimizes ringing due to

possible mismatched impedances on the output trace. Series termi-

nation at the source is generally required to provide transmission

line matching and/or to reduce current transients at the driver.

The value of the resistor (typically 10 Ω to 100 Ω) is dependent

on the board design and timing requirements. CMOS outputs

are also limited in terms of the capacitive load or trace length

that they can drive. Typically, trace lengths less than 3 inches are

recommended to preserve signal rise/fall times and signal integrity.

10Ω

MICROSTRIP

60.4Ω

1.0 INCH

CMOS

CMOS

Figure 26. Series Termination of CMOS Output

Termination at the far end of the PCB trace is a second option.

The CMOS outputs of the ADCLK854 do not supply enough

current to provide a full voltage swing with a low impedance

resistive, far end termination, as shown in Figure 27. The far end

termination network should match the PCB trace impedance and

provide the desired switching point. The reduced signal swing may