ADCLK854

Rev. 0 | Page 8 of 16

Pin No.

Mnemonic

Description

26

OUT7 (OUT7A)

True Side of Differential LVDS Output 7, or CMOS Output 7 on Channel A.

27

OUT6 (OUT6B)

Complementary Side of Differential LVDS Output 6, or CMOS Output 6 on Channel B.

28

OUT6 (OUT6A)

True Side of Differential LVDS Output 6, or CMOS Output 6 on Channel A.

31

OUT5 (OUT5B)

Complementary Side of Differential LVDS Output 5, or CMOS Output 5 on Channel B.

32

OUT5 (OUT5A)

True Side of Differential LVDS Output 5, or CMOS Output 5 on Channel A.

33

OUT4 (OUT4B)

Complementary Side of Differential LVDS Output 4, or CMOS Output 4 on Channel B.

34

OUT4 (OUT4A)

True Side of Differential LVDS Output 4, or CMOS Output 4 on Channel A.

35

NC

No Connect.

36

NC

No Connect.

39

OUT3 (OUT3B)

Complementary Side of Differential LVDS Output 3, or CMOS Output 3 on Channel B.

40

OUT3 (OUT3A)

True Side of Differential LVDS Output 3, or CMOS Output 3 on Channel A.

41

OUT2 (OUT2B)

Complementary Side of Differential LVDS Output 2, or CMOS Output 2 on Channel B.

42

OUT2 (OUT2A)

True Side of Differential LVDS Output 2, or CMOS Output 2 on Channel A.

45

OUT1 (OUT1B)

Complementary Side of Differential LVDS Output 1, or CMOS Output 1 on Channel B.

46

OUT1 (OUT1A)

True Side of Differential LVDS Output 1, or CMOS Output 1 on Channel A.

47

OUT0 (OUT0B)

Complementary Side of Differential LVDS Output 0, or CMOS Output 0 on Channel B.

48

OUT0 (OUT0A)

True Side of Differential LVDS Output 0, or CMOS Output 0 on Channel A.

(49)

EPAD

Exposed Paddle. The exposed paddle must be connected to GND.