ADCLK854

Rev. 0 | Page 12 of 16

FUNCTIONAL DESCRIPTION

The ADCLK854 accepts a clock input from one of two inputs

and distributes the selected clock to all output channels. The

outputs are grouped into three banks of four and can be set to

either LVDS or CMOS levels. This allows the selection of mul-

tiple logic configurations ranging from 12 LVDS to 24 CMOS

outputs, along with other combinations using both types of logic.

CLOCK INPUTS

The ADCLK854 differential inputs are internally self-biased.

The clock inputs have a resistor divider that sets the common-

mode level for the inputs. The complementary inputs are biased

about 30 mV lower than the true input to avoid oscillations if

the input signal stops. See Figure 20 for the equivalent input

circuit.

The inputs can be ac-coupled or dc-coupled. Table 8 displays a

guide for input logic compatibility. A single-ended input can be

accommodated by ac or dc coupling to one side of the differential

input; bypass the other input to ground with a capacitor.

Note that jitter performance degrades with low input slew rate,

as shown in Figure 11. See Figure 27 through Figure 32 for

different termination schemes.

9kΩ

9.5kΩ

9kΩ

10kΩ

10kΩ

8.5kΩ

CLKx

CLKx

GND

Figure 20. ADCLK854 Input Stage

AC-COUPLED INPUT APPLICATIONS

The ADCLK854 offers two options for ac coupling. The first

option requires no external components (excluding the dc

blocking capacitor), it allows the user to simply couple the

reference signal onto the clock input pins. For more infor-

mation, see Figure 29.

CLKx and CLKx through resistors. This method allows lower

impedance termination of signals at the ADCLK854 (for more

information, see Figure 32). The internal bias resistors remain

in parallel with the external biasing. However, the relatively

high impedance of the internal resistors allows the external

when offsetting the inputs; using only the internal biasing, as

previously mentioned, is not desirable.

CLOCK OUTPUTS

Each driver consists of a differential LVDS output or two single-

ended CMOS outputs (always in phase). When the LVDS driver

is enabled, the corresponding CMOS driver is in tristate; when

the CMOS driver is enabled, the corresponding LVDS driver is

powered down and tristated. Figure 21 and Figure 22 display

the equivalent output stage.

OUTx

OUTx

3.5mA

3.5mA

Figure 21. LVDS Output Simplified Equivalent Circuit

OUTA

OUTB

Figure 22. CMOS Output Equivalent Circuit

Table 8. Input Logic Compatibility

Supply (V)

Logic

Common Mode (V)

Output Swing (V)

AC-Coupled

DC-Coupled

3.3

CML

2.9

0.8

Yes

Not allowed

2.5

CML

2.1

0.8

Yes

Not allowed

1.8

CML

1.4

0.8

Yes

Yes

3.3

CMOS

1.65

3.3

Not allowed

Not allowed

2.5

CMOS

1.25

2.5

Not allowed

Not allowed

1.8

CMOS

0.9

1.8

Yes

Yes

1.5

HSTL

0.75

0.75

Yes

Yes

LVDS

1.25

0.4

Yes

Yes

3.3

LVPECL

2.0

0.8

Yes

Not allowed

2.5

LVPECL

1.2

0.8

Yes

Yes

1.8

LVPECL

0.5

0.8

Yes

Yes