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STM32F107VC 数据表(PDF) 89 Page - STMicroelectronics |
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STM32F107VC 数据表(HTML) 89 Page - STMicroelectronics |
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89 / 95 page  STM32F105xx, STM32F107xx Applicative block diagrams Doc ID 15274 Rev 4 89/95 A.4 USB OTG FS interface + Ethernet/I2S interface solutions With the clock tree implemented on the STM32F107xx, only one crystal is required to work with both the USB (host/device/OTG) and the Ethernet (MII/RMII) interfaces. Figure 48 illustrate the solution. Figure 48. USB OTG FS + Ethernet solution With the clock tree implemented on the STM32F107xx, only one crystal is required to work with both the USB (host/device/OTG) and the I2S (Audio) interfaces. Figure 49 illustrate the solution. Figure 49. USB OTG FS + I2S (Audio) solution 25 MHz XTAL OTG 48 MHz MCO PLL2 x8 MCU MCO Div by 5 sel Div by 3 PLL x9 VCO Out x18 Div by 5 Ethernet PHY PHY STM32F107 Cortex-M3 core Up to 50 MHz I2S PLL3 x10 SCLK MCLK 2% accuracy error up to 72 MHz ai15662b sel 14.7456 MHz XTAL OTG 47.9232 MHz MCO PLL2 x12 MCU MCO Div by 4 sel Div by 3 PLL x6.5 VCO Out x13 Div by 4 PHY STM32F105/STM32F107 Cortex-M3 core Up to 147.456 MHz I2S PLL3 VCO Out x40 SCLK MCLK Less than 0.5% accuracy error on MCLK and SCLK Up to 71.88 MHz ai15663b 0.16% accuracy error |
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