STM32F107VC datasheet(14/95 Pages) STMICROELECTRONICS

14 / 95 page

Description

STM32F105xx, STM32F107xx

14/95

Doc ID 15274 Rev 4

2.3.6

External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 20 edge detector lines used to generate

interrupt/event requests. Each line can be independently configured to select the trigger

event (rising edge, falling edge, both) and can be masked independently. A pending register

maintains the status of the interrupt requests. The EXTI can detect an external line with a

pulse width shorter than the Internal APB2 clock period. Up to 80 GPIOs can be connected

to the 16 external interrupt lines.

2.3.7

Clocks and startup

System clock selection is performed on startup, however, the internal RC 8 MHz oscillator is

selected as default CPU clock on reset. An external 3-25 MHz clock can be selected, in

which case it is monitored for failure. If failure is detected, the system automatically switches

back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full

interrupt management of the PLL clock entry is available when necessary (for example with

failure of an indirectly used external oscillator).

A single 25 MHz crystal can clock the entire system including the ethernet and USB OTG

FS peripherals. Several prescalers and PLLs allow the configuration of the AHB frequency,

the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum

frequency of the AHB and the high speed APB domains is 72 MHz. The maximum allowed

frequency of the low speed APB domain is 36 MHz. Refer to Figure 48: USB OTG FS +

Ethernet solution on page 89.

The advanced clock controller clocks the core and all peripherals using a single crystal or

oscillator. In order to achieve audio class performance, an audio crystal can be used. In this

case, the I2S master clock can generate all standard sampling frequencies from 8 kHz to

96 kHz with less than 0.5% accuracy error. Refer to Figure 49: USB OTG FS + I2S (Audio)

solution on page 89.

To configure the PLLs, please refer to Table 61 on page 90, which provides PLL

configurations according to the application type.

2.3.8

Boot modes

At startup, boot pins are used to select one of three boot options:

Boot from User Flash

Boot from System Memory

Boot from embedded SRAM

The boot loader is located in System Memory. It is used to reprogram the Flash memory by

using USART1, USART2 (remapped), CAN2 (remapped) or USB OTG FS in device mode

(DFU: device firmware upgrade). For remapped signals refer to Table 5: Pin definitions.

The USART peripheral operates with the internal 8 MHz oscillator (HSI), however the CAN

and USB OTG FS can only function if an external 8 MHz, 14.7456 MHz or 25 MHz clock

(HSE) is present.

For full details about the boot loader, please refer to AN2662.

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