AT25DF161 datasheet(15/60 Pages) ATMEL

15 / 60 page

3687C–DFLASH–7/09

AT25DF161 [Preliminary]

Figure 8-4.

Dual-Input Page Program

8.3

Block Erase

A block of 4, 32, or 64 Kbytes can be erased (all bits set to the logical “1” state) in a single oper-

ation by using one of three different opcodes for the Block Erase command. An opcode of 20h is

used for a 4-Kbyte erase, an opcode of 52h is used for a 32-Kbyte erase, and an opcode of D8h

is used for a 64-Kbyte erase. Before a Block Erase command can be started, the Write Enable

command must have been previously issued to the device to set the WEL bit of the Status Reg-

ister to a logical “1” state.

To perform a Block Erase, the CS pin must first be asserted and the appropriate opcode (20h,

52h, or D8h) must be clocked into the device. After the opcode has been clocked in, the three

address bytes specifying an address within the 4-, 32-, or 64-Kbyte block to be erased must be

clocked in. Any additional data clocked into the device will be ignored. When the CS pin is deas-

serted, the device will erase the appropriate block. The erasing of the block is internally self-

timed and should take place in a time of tBLKE.

Since the Block Erase command erases a region of bytes, the lower order address bits do not

need to be decoded by the device. Therefore, for a 4-Kbyte erase, address bits A11-A0 will be

ignored by the device and their values can be either a logical “1” or “0”. For a 32-Kbyte erase,

address bits A14-A0 will be ignored, and for a 64-Kbyte erase, address bits A15-A0 will be

ignored by the device. Despite the lower order address bits not being decoded by the device, the

complete three address bytes must still be clocked into the device before the CS pin is deas-

serted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits);

otherwise, the device will abort the operation and no erase operation will be performed.

If the address specified by A23-A0 points to a memory location within a sector that is in the pro-

tected or locked down state, then the Block Erase command will not be executed, and the device

will return to the idle state once the CS pin has been deasserted.

The WEL bit in the Status Register will be reset back to the logical “0” state if the erase cycle

aborts due to an incomplete address being sent, the CS pin being deasserted on uneven byte

boundaries, or because a memory location within the region to be erased is protected or locked

down.

While the device is executing a successful erase cycle, the Status Register can be read and will

indicate that the device is busy. For faster throughput, it is recommended that the Status Regis-

ter be polled rather than waiting the tBLKE time to determine if the device has finished erasing. At

some point before the erase cycle completes, the WEL bit in the Status Register will be reset

back to the logical “0” state.

SCK

SOI

MSB

10100010

410 11

812

37 38

31 32

29 30

OPCODE

AAAA

AAA

MSB

ADDRESS BITS A23-A0

INPUT

DATA BYTE 1

MSB

INPUT

DATA BYTE n

INPUT

DATA BYTE 2

HIGH-IMPEDANCE

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