AT25DF161 datasheet(17/60 Pages) ATMEL

17 / 60 page

3687C–DFLASH–7/09

AT25DF161 [Preliminary]

Figure 8-6.

Chip Erase

8.5

Program/Erase Suspend

In some code plus data storage applications, it is often necessary to process certain high-level

system interrupts that require relatively immediate reading of code or data from the Flash mem-

ory. In such an instance, it may not be possible for the system to wait the microseconds or

milliseconds required for the Flash memory to complete a program or erase cycle. The Pro-

gram/Erase Suspend command allows a program or erase operation in progress to a particular

64-Kbyte sector of the Flash memory array to be suspended so that other device operations can

be performed. For example, by suspending an erase operation to a particular sector, the system

can perform functions such as a program or read operation within another 64-Kbyte sector in the

device. Other device operations, such as a Read Status Register, can also be performed while a

program or erase operation is suspended. Table 8-1 outlines the operations that are allowed and

not allowed during a program or erase suspend.

Since the need to suspend a program or erase operation is immediate, the Write Enable com-

mand does not need to be issued prior to the Program/Erase Suspend command being issued.

Therefore, the Program/Erase Suspend command operates independently of the state of the

WEL bit in the Status Register.

To perform a Program/Erase Suspend, the CS pin must first be asserted and the opcode of B0h

must be clocked into the device. No address bytes need to be clocked into the device, and any

data clocked in after the opcode will be ignored. When the CS pin is deasserted, the program or

erase operation currently in progress will be suspended within a time of tSUSP. The Program Sus-

pend (PS) bit or the Erase Suspend (ES) bit in the Status Register will then be set to the logical

“1” state to indicate that the program or erase operation has been suspended. In addition, the

RDY/BSY bit in the Status Register will indicate that the device is ready for another operation.

The complete opcode must be clocked into the device before the CS pin is deasserted, and the

CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, no

suspend operation will be performed.

Read operations are not allowed to a 64-Kbyte sector that has had its program or erase opera-

tion suspended. If a read is attempted to a suspended sector, then the device will output

undefined data. Therefore, when performing a Read Array operation to an unsuspended sector

and the device’s internal address counter increments and crosses the sector boundary to a sus-

pended sector, the device will then start outputting undefined data continuously until the address

counter increments and crosses a sector boundary to an unsuspended sector.

A program operation is not allowed to a sector that has been erase suspended. If a program

operation is attempted to an erase suspended sector, then the program operation will abort and

the WEL bit in the Status Register will be reset back to the logical “0” state. Likewise, an erase

SCK

MSB

CCCCCCCC

OPCODE

HIGH-IMPEDANCE

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