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AT25DF161 数据表(PDF) 37 Page - ATMEL Corporation |
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AT25DF161 数据表(HTML) 37 Page - ATMEL Corporation |
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37 / 60 page ![]() 37 3687C–DFLASH–7/09 AT25DF161 [Preliminary] Notes: 1. Only bits 4 and 3 of Status Register Byte 2 will be modified when using the Write Status Register Byte 2 command. 2. R/W = Readable and writeable R = Readable only 11.1.1 SPRL Bit The SPRL bit is used to control whether the Sector Protection Registers can be modified or not. When the SPRL bit is in the logical “1” state, all Sector Protection Registers are locked and can- not be modified with the Protect Sector and Unprotect Sector commands (the device will ignore these commands). In addition, the Global Protect and Global Unprotect features cannot be per- formed. Any sectors that are presently protected will remain protected, and any sectors that are presently unprotected will remain unprotected. When the SPRL bit is in the logical “0” state, all Sector Protection Registers are unlocked and can be modified (the Protect Sector and Unprotect Sector commands, as well as the Global Pro- tect and Global Unprotect features, will be processed as normal). The SPRL bit defaults to the logical “0” state after device power-up. The Reset command has no effect on the SPRL bit. The SPRL bit can be modified freely whenever the WP pin is deasserted. However, if the WP pin is asserted, then the SPRL bit may only be changed from a logical “0” (Sector Protection Regis- ters are unlocked) to a logical “1” (Sector Protection Registers are locked). In order to reset the SPRL bit back to a logical “0” using the Write Status Register Byte 1 command, the WP pin will have to first be deasserted. The SPRL bit is the only bit of Status Register Byte 1 that can be user modified via the Write Sta- tus Register Byte 1 command. 11.1.2 EPE Bit The EPE bit indicates whether the last erase or program operation completed successfully or not. If at least one byte during the erase or program operation did not erase or program properly, then the EPE bit will be set to the logical “1” state. The EPE bit will not be set if an erase or pro- Table 11-2. Status Register Format – Byte 2 Bit(1) Name Type(2) Description 7 RES Reserved for future use R 0 Reserved for future use. 6 RES Reserved for future use R 0 Reserved for future use. 5 RES Reserved for future use R 0 Reserved for future use. 4 RSTE Reset Enabled R/W 0 Reset command is disabled (default). 1 Reset command is enabled. 3 SLE Sector Lockdown Enabled R/W 0 Sector Lockdown and Freeze Sector Lockdown State commands are disabled (default). 1 Sector Lockdown and Freeze Sector Lockdown State commands are enabled. 2 PS Program Suspend Status R 0 No sectors are program suspended (default). 1 A sector is program suspended. 1 ES Erase Suspend Status R 0 No sectors are erase suspended (default). 1 A sector is erase suspended. 0 RDY/BSY Ready/Busy Status R 0 Device is ready. 1 Device is busy with an internal operation. |
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