AT25DF161 datasheet(26/60 Pages) ATMEL

26 / 60 page

3687C–DFLASH–7/09

AT25DF161 [Preliminary]

If the desire is to only change the SPRL bit without performing a Global Protect or Global Unpro-

tect, then the system can simply write a 0Fh to the first byte of the Status Register to change the

SPRL bit from a logical “1” to a logical “0” provided the WP pin is deasserted. Likewise, the sys-

tem can write an F0h to change the SPRL bit from a logical “0” to a logical “1” without affecting

the current sector protection status (no changes will be made to the Sector Protection

Registers).

When writing to the first byte of the Status Register, bits 5, 4, 3, and 2 will not actually be modi-

fied but will be decoded by the device for the purposes of the Global Protect and Global

Unprotect functions. Only bit 7, the SPRL bit, will actually be modified. Therefore, when reading

the first byte of the Status Register, bits 5, 4, 3, and 2 will not reflect the values written to them

but will instead indicate the status of the WP pin and the sector protection status. Please refer to

“Read Status Register” on page 35 and Table 11-1 on page 36 for details on the Status Register

format and what values can be read for bits 5, 4, 3, and 2.

9.6

Read Sector Protection Registers

The Sector Protection Registers can be read to determine the current software protection status

of each sector. Reading the Sector Protection Registers, however, will not determine the status

of the WP pin.

To read the Sector Protection Register for a particular sector, the CS pin must first be asserted

and the opcode of 3Ch must be clocked in. Once the opcode has been clocked in, three address

bytes designating any address within the sector must be clocked in. After the last address byte

has been clocked in, the device will begin outputting data on the SO pin during every subse-

quent clock cycle. The data being output will be a repeating byte of either FFh or 00h to denote

the value of the appropriate Sector Protection Register.

At clock frequencies above fCLK, the first byte of data output will not be valid. Therefore, if operat-

ing at clock frequencies above fCLK, at least two bytes of data must be clocked out from the

device in order to determine the correct status of the appropriate Sector Protection Register.

Deasserting the CS pin will terminate the read operation and put the SO pin into a high-imped-

ance state. The CS pin can be deasserted at any time and does not require that a full byte of

data be read.

In addition to reading the individual Sector Protection Registers, the Software Protection Status

(SWP) bits in the Status Register can be read to determine if all, some, or none of the sectors

are software protected (refer to “Read Status Register” on page 35 for more details).

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