AT25DF161 datasheet(16/60 Pages) ATMEL

16 / 60 page

3687C–DFLASH–7/09

AT25DF161 [Preliminary]

The device also incorporates an intelligent erase algorithm that can detect when a byte location

fails to erase properly. If an erase error occurs, it will be indicated by the EPE bit in the Status

Figure 8-5.

Block Erase

8.4

Chip Erase

The entire memory array can be erased in a single operation by using the Chip Erase command.

Before a Chip Erase command can be started, the Write Enable command must have been pre-

viously issued to the device to set the WEL bit of the Status Register to a logical “1” state.

Two opcodes, 60h and C7h, can be used for the Chip Erase command. There is no difference in

device functionality when utilizing the two opcodes, so they can be used interchangeably. To

perform a Chip Erase, one of the two opcodes (60h or C7h) must be clocked into the device.

Since the entire memory array is to be erased, no address bytes need to be clocked into the

device, and any data clocked in after the opcode will be ignored. When the CS pin is deas-

serted, the device will erase the entire memory array. The erasing of the device is internally self-

timed and should take place in a time of tCHPE.

The complete opcode must be clocked into the device before the CS pin is deasserted, and the

CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, no

erase will be performed. In addition, if any sector of the memory array is in the protected or

locked down state, then the Chip Erase command will not be executed, and the device will return

to the idle state once the CS pin has been deasserted. The WEL bit in the Status Register will be

reset back to the logical “0” state if the CS pin is deasserted on uneven byte boundaries or if a

sector is in the protected or locked down state.

While the device is executing a successful erase cycle, the Status Register can be read and will

indicate that the device is busy. For faster throughput, it is recommended that the Status Regis-

ter be polled rather than waiting the tCHPE time to determine if the device has finished erasing. At

some point before the erase cycle completes, the WEL bit in the Status Register will be reset

back to the logical “0” state.

The device also incorporates an intelligent erase algorithm that can detect when a byte location

fails to erase properly. If an erase error occurs, it will be indicated by the EPE bit in the Status

SCK

MSB

CCCCCCCC

410 11

812

29 30

27 28

OPCODE

AAAA

AAA

ADDRESS BITS A23-A0

HIGH-IMPEDANCE

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