ATmega16HVB datasheet(63/273 Pages) ATMEL

63 / 273 page

8042A–AVR–07/09

ATmega16HVB/32HVB

14.2

High Voltage Ports as General Digital I/O

The high voltage ports are high voltage tolerant open collector output ports. In addition they can

be used as general digital inputs. Figure 14-2 shows a functional description of one output port

pin, here generically called Pxn.

Figure 14-2. General High Voltage Digital I/O

(1)

Notes:

1. WRx, RRx and RPx are common to all pins within the same port. clkI/O and SLEEP are com-

mon to all ports.

2. The High Voltage Digital Input is not present on PC5.

14.2.1

Configuring the Pin

Each port pin consist of two register bits: PORTxn and PINxn. As shown in ”Register Descrip-

tion” on page 66, the PORTxn bits are accesed at the PORTx I/O address, and the PINxn bits at

the PINx I/O address.

If PORTxn is written logic one, the port pin is driven low (zero). If PORTxn is written logic zero,

the port pin is tri-stated. The port pins are tri-stated when a reset condition becomes active, even

if no clocks are running.

14.2.2

Reading the Pin

The port pin can be read through the PINxn Register bit. As shown in Figure 14-2, the PINxn

bility if the physical pin changes value near the edge of the internal clock, but it also introduces a

delay.

WRx

SLEEP:

SLEEP CONTROL

clkI/O:

I/O CLOCK

SLEEP

Pxn

PORTxn

CLR

RRx

SYNCHRONIZER

CLR

PINxn

clk

I/O

SET

CLR

RESET

RPx

RRx:

READ PORTx REGISTER

WRx:

WRITE PORTx REGISTER

RPx:

READ PINx REGISTER

HIGH VOLTAGE DIGITAL INPUT (2)

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