ATmega16HVB datasheet(29/273 Pages) ATMEL

29 / 273 page

8042A–AVR–07/09

ATmega16HVB/32HVB

neither the clock frequency corresponding to the previous setting, nor the clock frequency corre-

sponding to the new setting.

The ripple counter that implements the prescaler runs at the frequency of the undivided clock,

and may be faster than the CPU's clock frequency. It is not possible to determine the state of the

prescaler, and the exact time it takes to switch from one clock division to the other cannot be

exactly predicted. From the time the CLKPS values are written, it takes between T1 + T2 and T1

+ 2*T2 before the new clock frequency is active. In this interval, two active clock edges are pro-

duced. Here, T1 is the previous clock period, and T2 is the period corresponding to the new

prescaler setting.

To avoid unintentional changes of clock frequency, a special write procedure must be followed

to change the CLKPS bits:

Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in

CLKPR to zero.

Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.

Interrupts must be disabled when changing prescaler setting to make sure the write procedure is

not interrupted.

9.6

VADC Clock Prescaler

The VADC clock will be automatically prescaled relative to the System Clock Prescaler settings,

see ”System Clock Prescaler” on page 28. Depending on the Clock Prescale Select bits,

CLKPS1..0, the VADC clock, clk

VADC, will be prescaled by 8, 4, 2 or 1 as shown in Table 9-5 on

page 33.

9.7

OSI – Oscillator Sampling Interface

9.7.1

Features

• Runtime selectable oscillator input (Slow RC or ULP RC Oscillator)

• 7 bit prescaling of the selected oscillator

• Software read access to the phase of the prescaled clock

• Input capture trigger source for Timer/Counter0

9.7.2

Overview

The Oscillator Sampling Interface (OSI) enables sampling of the Slow RC and Ultra Low Power

RC (ULP) oscillators in ATmega16HVB/32HVB. OSI can be used to calibrate the Fast RC Oscil-

lator runtime with high accuracy. OSI can also provide an accurate reference for compensating

the ULP Oscillator frequency drift. This is useful for modules with high-precision requirements,

such as the Coulomb Counter.

The prescaled oscillator phase can be continuously read by the CPU through the OSICSR regis-

ter. In addition, the input capture function of Timer/Counter0 can be set up to trigger on the rising

edge of the prescaled clock. This enables accurate measurements of the oscillator frequencies

relative to the Fast RC Oscillator.

A simplified block diagram of the Oscillator Sampling Interface is shown in Figure 9-2 on page

30.

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