ATmega16HVB datasheet(39/273 Pages) ATMEL

39 / 273 page

8042A–AVR–07/09

ATmega16HVB/32HVB

For analog input pins, the digital input buffer should be disabled at all times. An analog signal

level close to V

REG/2 on an input pin can cause significant current even in active mode. Digital

input buffers can be disabled by writing to the Digital Input Disable Register. Refer to ”DIDR0 –

Digital Input Disable Register 0” on page 122 for details.

10.7.3

On-chip Debug System

A programmed DWEN Fuse enables some parts of the clock system to be running in all sleep

modes. This will increase the power consumption while in sleep. Thus, the DWEN Fuse should

be disabled when debugWire is not used.

10.7.4

Battery Protection

If one of the Battery Protection features is not needed by the application, this feature should be

disabled, see “BPCR – Battery Protection Control Register” on page 141. The current consump-

tion in the Battery Protection circuitry is only significant in Power-save mode. Disabling both

FETs will automatically disable the Battery Protection module in order to save power. The band-

gap reference should always be enabled whenever Battery Protection is enabled.

10.7.5

Voltage ADC

If enabled, the V-ADC will consume power independent of sleep mode. To save power, the V-

ADC should be disabled when not used, and before entering Power-save sleep mode. See

”Voltage ADC – 7-channel General Purpose 12-bit Sigma-Delta ADC” on page 117 for details on

V-ADC operation.

10.7.6

Coulomb Counter

If enabled, the CC-ADC will consume power independent of sleep mode. To save power, the

CC-ADC should be disabled when not used, or set in Regular Current detection mode. See

”Coulomb Counter - Dedicated Fuel Gauging Sigma-delta ADC” on page 108 for details on CC-

ADC operation.

10.7.7

Bandgap Voltage Reference

If enabled, the Bandgap reference will consume power independent of sleep mode. To save

power, the Bandgap reference should be disabled when not used as reference for the Voltage

ADC, the Coloumb Counter or Battery Protection. See ”Voltage Reference and Temperature

Sensor” on page 123 for details.

10.8

10.8.1

SMCR – Sleep Mode Control Register

The Sleep Mode Control Register contains control bits for power management.

• Bits 7:4 – Res: Reserved Bits

These bits are reserved bits in the ATmega16HVB/32HVB, and will always read as zero.

• Bits 3:1 – SM2:0: Sleep Mode Select Bits 2, 1 and 0

Bit

765

432

0x33 (0x53)

–

SM2

SM1

SM0

SMCR

Read/Write

R/W

Initial Value

ATmega16HVB 数据表(PDF) 39 Page - ATMEL Corporation

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