ATmega16HVB datasheet(19/273 Pages) ATMEL

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8042A–AVR–07/09

ATmega16HVB/32HVB

Figure 8-3.

On-chip Data SRAM Access Cycles

8.4

EEPROM Data Memory

The ATmega16HVB/32HVB contains 512/1K bytes of data EEPROM memory. It is organized as

a separate data space, in which single bytes can be read and written. The EEPROM has an

endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the

CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM

Data Register, and the EEPROM Control Register.

For a detailed description of EEPROM programming, see page 211 and page 216 respectively.

8.4.1

EEPROM Read/Write Access

The EEPROM Access Registers are accessible in the I/O space.

The write access time for the EEPROM is given in Table 8-1 on page 21. A self-timing function,

however, lets the user software detect when the next byte can be written. If the user code con-

tains instructions that write the EEPROM, some precautions must be taken.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.

Refer to the description of the EEPROM Control Register for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is

executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next

instruction is executed.

8.5

I/O Memory

The I/O space definition of the ATmega16HVB/32HVB is shown in ”Register Summary” on page

254.

All ATmega16HVB/32HVB I/Os and peripherals are placed in the I/O space. All I/O locations

may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between

the 32 general purpose working registers and the I/O space. I/O Registers within the address

range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these regis-

ters, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to

the instruction set section for more details. When using the I/O specific commands IN and OUT,

clk

Data

Address

Address valid

Compute Address

CPU

Memory Access Instruction

Next Instruction

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