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ATmega16HVB 数据表(PDF) 44 Page - ATMEL Corporation |
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ATmega16HVB 数据表(HTML) 44 Page - ATMEL Corporation |
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44 / 273 page ![]() 44 8042A–AVR–07/09 ATmega16HVB/32HVB Figure 11-2. Powering up ATmega16HVB/32HVB 11.2.2 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see Table 32-3 on page 230) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage – V RST – on its positive edge, the delay counter starts the MCU after the Time-out period – t TOUT – has expired. Figure 11-3. External Reset During Operation 11.2.3 Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period t TOUT. Refer to page 46 for details on operation of the Watchdog Timer. Power-off SLEEP_MODE POR V BATT INTERNAL_RESET t TOUT Reset Active V POT V REG 3.3 V |
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