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ATmega16HVB 数据表(PDF) 121 Page - ATMEL Corporation |
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ATmega16HVB 数据表(HTML) 121 Page - ATMEL Corporation |
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121 / 273 page ![]() 121 8042A–AVR–07/09 ATmega16HVB/32HVB VADSC will read as one as long as the conversion is not finished. When the conversion is com- plete, it returns to zero. Writing zero to this bit has no effect. VADSC will automatically be cleared when the VADEN bit is written to zero. • Bit 1 – VADCCIF: V-ADC Conversion Complete Interrupt Flag This bit is set when a V-ADC conversion completes and the data registers are updated. The V- ADC Conversion Complete Interrupt is executed if the VADCCIE bit and the I-bit in SREG are set. VADCCIF is cleared by hardware when executing the corresponding interrupt handling vec- tor. Alternatively, VADCCIF is cleared by writing a logical one to the flag. Beware that if doing a Read-Modify-Write on VADCSR, a pending interrupt can be lost. • Bit 0 – VADCCIE: V-ADC Conversion Complete Interrupt Enable When this bit is written to one and the I-bit in SREG is set, the V-ADC Conversion Complete Interrupt is activated. 20.4.3 VADCL and VADCH – V-ADC Data Register When a V-ADC conversion is complete, the result is found in these two registers. To ensure that correct data is read, both high and low byte data registers should be read before starting a new conversion. • VADC11:0: V-ADC Conversion Result These bits represent the result from the conversion. To obtain the best absolute accuracy for the cell voltage measurements, gain and offset com- pensation is required. Factory calibration values are stored in the device signature row, refer to section ”Reading the Signature Row from Software” on page 199 for details. The cell voltage in mV is given by: The voltage on the ADCn is given by: When performing a Vtemp conversion, the result must be adjusted by the factory calibration value stored in the signature row, refer to section ”Reading the Signature Row from Software” on page 199 for details. The absolute temperature in Kelvin is given by: Bit 15 14 13 12 11 10 9 8 (0x79) – – – – VADC[11:8] VADCH (0x78) VADC[7:0] VADCL 76 5 4 3 2 1 0 Read/Write R R R R R R R R RR R R R R R R Initial Value 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 Cell n[mV] (VADCH/L VADC Cell nOffset) VADC Cell n Gain Calibration Word ⋅ – 16384 -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- = ADCn[mV] 1 10 ------ (VADCH/L VADC ADCn Offset) VADC ADCn Gain Calibration Word ⋅ – 16384 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ⋅ = |
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