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ATmega16HVB 数据表(PDF) 131 Page - ATMEL Corporation |
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ATmega16HVB 数据表(HTML) 131 Page - ATMEL Corporation |
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131 / 273 page ![]() 131 8042A–AVR–07/09 ATmega16HVB/32HVB • When disabling the Charge-FET the Charger Detect module is automatically enabled and a charger appear to be connected. 22.4 Register Description 22.4.1 CHGDCSR - Charger Detect Control and Status Register • Bit 7:5 - Res: Reserved These bits are reserved bits and will always read as zero. • Bit 4 - BATTPVL: BATT pin Voltage Level BATTPVL will read one as long when the Charger Detect module is enabled and the BATT pin voltage is above the VPOT level. Otherwise the BATTPVL will read zero. • Bit 3:2 - CHGDISC1:0: Charger Detect Interrupt Sense Control Edges in the CHARGER_PRESENT signal shown in Figure 22-1 on page 129 are used to acti- vate a Charger Detect Interrupt if the SREG I-flag and the interrupt enable bit in CHGDCSR are set. By writing the CHGDISC bits to the values shown in Table 22-1 on page 131 the condition generating interrupt is configured. When changing the CHGDISC bits, an interrupt can occur. Therefore, it is recommended to first disable the Interrupt by clearing its CHGDIE bit in the CHGDICSR Register. Finally, the Charger Detect interrupt flag should be cleared by writing a logical one to CHGDIF bit before the interrupt is re-enabled. • Bit 1 - CHGDIF: Charger Detect Interrupt Flag Depending on the configuration of the CHGDISC bits in the CHGDCSR, this bit is set when a charger is either connected or disconnected. The Charger Detect Interrupt is executed if the CHGDIE bit and the I-bit in SREG are set. This bit is cleared by hardware when executing the corresponding interrupt handling vector or alternatively by writing a logical one to the CHGDIF. It is recommended to write this bit to one when setting CHGDIE. • Bit 0 - CHGDIE: Charger Detect Interrupt Enable When the CHGDIE bit is set (one), and the I-bit in the Status Register is set (one), the Charger Detect Interrupt is enabled. Bit 7 6 5 43210 (0xD4) - - - BATTPVL CHGDISC1 CHGDISC0 CHGDIF CHGDIE CHGDCSR Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 00000 Table 22-1. Charger Detect Interrupt Sense Control. CHGISC1:0 Detection 00 Charger Connect 01 Charger Disconnect 10 Charger Connect/Disconnect 11 None |
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