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ATmega16HVB 数据表(PDF) 162 Page - ATMEL Corporation |
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ATmega16HVB 数据表(HTML) 162 Page - ATMEL Corporation |
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162 / 273 page  162 8042A–AVR–07/09 ATmega16HVB/32HVB 27.5 Overview of the TWI Module The TWI module is comprised of several submodules, as shown in Figure 27-9. The shaded reg- isters are accessible through the AVR data bus. Figure 27-9. Overview of the TWI Module 27.5.1 SCL and SDA Pins These pins interface the AVR TWI with the rest of the MCU system. The output drivers contain a slew-rate limiter in order to conform to the TWI specification. The input stages contain a spike suppression unit removing spikes shorter than 50 ns. Address Register (TWAR) Address Match Unit Address Comparator Control Unit Status Register (TWSR) State Machine and Status Control SCL Slew-rate Control Spike Filter SDA Slew-rate Control Spike Filter Bit Rate Generator Bit Rate Register (TWBR) Prescaler Bus Interface Unit START / STOP Control Arbitration Detection Ack Spike Suppression Address/Data Shift Register (TWDR) Control Register (TWCR) |
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