ATmega16HVB datasheet(178/273 Pages) ATMEL

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178

8042A–AVR–07/09

ATmega16HVB/32HVB

27.7.4

Slave Transmitter Mode

In the Slave Transmitter mode, a number of data bytes are transmitted to a master receiver (see

Figure 27-17). All the status codes mentioned in this section assume that the prescaler bits are

zero or are masked to zero.

Figure 27-17. Data Transfer in Slave Transmitter Mode

To initiate the Slave Transmitter mode, TWAR and TWCR must be initialized as follows:

The upper seven bits are the address to which the Two-wire Serial Interface will respond when

addressed by a master. If the LSB is set, the TWI will respond to the general call address (0x00),

otherwise it will ignore the general call address.

TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable

the acknowledgment of the device’s own slave address or the general call address. TWSTA and

TWSTO must be written to zero.

When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its own

slave address (or the general call address if enabled) followed by the data direction bit. If the

direction bit is “1” (read), the TWI will operate in ST mode, otherwise SR mode is entered. After

its own slave address and the write bit have been received, the TWINT flag is set and a valid

status code can be read from TWSR. The status code is used to determine the appropriate soft-

ware action. The appropriate action to be taken for each status code is detailed in Table 27-5.

The Slave Transmitter mode may also be entered if arbitration is lost while the TWI is in the

Master mode (see state 0xB0).

If the TWEA bit is written to zero during a transfer, the TWI will transmit the last byte of the trans-

fer. State 0xC0 or state 0xC8 will be entered, depending on whether the master receiver

transmits a NACK or ACK after the final byte. The TWI is switched to the not addressed Slave

mode, and will ignore the master if it continues the transfer. Thus the master receiver receives

all “1” as serial data. State 0xC8 is entered if the master demands additional data bytes (by

transmitting ACK), even though the slave has transmitted the last byte (TWEA zero and expect-

ing NACK from the master).

TWAR

TWA6

TWA5

TWA4

TWA3

TWA2

TWA1

TWA0

TWGCE

Value

Device’s Own Slave Address

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

Value

100

Device 3

Device n

SDA

SCL

........

BUS

Device 2

MASTER

RECEIVER

Device 1

SLAVE

TRANSMITTER

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