ATtiny10 datasheet(66/168 Pages) ATMEL

66 / 168 page

8127C–AVR–10/09

ATtiny4/5/9/10

operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes

are preferred for motor control applications.

The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined

by either ICR0 or OCR0A. The minimum resolution allowed is 2-bit (ICR0 or OCR0A set to

0x0003), and the maximum resolution is 16-bit (ICR0 or OCR0A set to MAX). The PWM resolu-

tion in bits can be calculated by using the following equation:

In phase correct PWM mode the counter is incremented until the counter value matches either

one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM03:0 = 1, 2, or 3), the value in ICR0

(WGM03:0 = 10), or the value in OCR0A (WGM03:0 = 11). The counter has then reached the

TOP and changes the count direction. The TCNT0 value will be equal to TOP for one timer clock

cycle. The timing diagram for the phase correct PWM mode is shown on Figure 11-10 on page

66. The figure shows phase correct PWM mode when OCR0A or ICR0 is used to define TOP.

The TCNT0 value is in the timing diagram shown as a histogram for illustrating the dual-slope

operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal

line marks on the TCNT0 slopes represent compare matches between OCR0x and TCNT0. The

OC0x interrupt flag will be set when a compare match occurs.

Figure 11-10. Phase Correct PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. When

either OCR0A or ICR0 is used for defining the TOP value, the OC0A or ICF0 flag is set accord-

ingly at the same timer clock cycle as the OCR0x Registers are updated with the double buffer

value (at TOP). The interrupt flags can be used to generate an interrupt each time the counter

reaches the TOP or BOTTOM value.

When changing the TOP value the program must ensure that the new TOP value is higher or

equal to the value of all of the Compare Registers. If the TOP value is lower than any of the

RPCPWM

TOP 1

()

log

()

log

-----------------------------------

OCRnx/TOP Update and

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

TOVn Interrupt Flag Set

(Interrupt on Bottom)

TCNTn

Period

OCnx

(COMnx1:0 = 2)

(COMnx1:0 = 3)

ATtiny10 数据表(PDF) 66 Page - ATMEL Corporation

ATtiny10 数据表(HTML) 66 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载