ATtiny10 datasheet(19/168 Pages) ATMEL

19 / 168 page

8127C–AVR–10/09

ATtiny4/5/9/10

6.2.3

Internal 128 kHz Oscillator

The internal 128 kHz oscillator is a low power oscillator providing a clock of 128 kHz. The fre-

quency depends on supply voltage, temperature and batch variations. This clock may be select

as the main clock by setting the CLKMS[1:0] bits in CLKMSR to 0b01.

6.2.4

Switching Clock Source

The main clock source can be switched at run-time using the “CLKMSR – Clock Main Settings

that no glitch occurs in the main clock.

6.2.5

Default Clock Source

The calibrated internal 8 MHz oscillator is always selected as main clock when the device is

powered up or has been reset. The synchronous system clock is the main clock divided by 8,

controlled by the System Clock Prescaler. The Clock Prescaler Select Bits can be written later to

change the system clock frequency. See “System Clock Prescaler”.

6.3

System Clock Prescaler

The system clock is derived from the main clock via the System Clock Prescaler. The system

clock can be divided by setting the “CLKPSR – Clock Prescale Register” on page 22. The sys-

tem clock prescaler can be used to decrease power consumption at times when requirements

for processing power is low or to bring the system clock within limits of maximum frequency. The

prescaler can be used with all main clock source options, and it will affect the clock frequency of

the CPU and all synchronous peripherals.

The System Clock Prescaler can be used to implement run-time changes of the internal clock

frequency while still ensuring stable operation.

6.3.1

Switching Prescaler Setting

When switching between prescaler settings, the system clock prescaler ensures that no glitch

occurs in the system clock and that no intermediate frequency is higher than neither the clock

frequency corresponding the previous setting, nor the clock frequency corresponding to the new

setting.

The ripple counter that implements the prescaler runs at the frequency of the main clock, which

may be faster than the CPU's clock frequency. Hence, it is not possible to determine the state of

the prescaler - even if it were readable, and the exact time it takes to switch from one clock divi-

sion to another cannot be exactly predicted.

From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before the

new clock frequency is active. In this interval, two active clock edges are produced. Here, T1 is

the previous clock period, and T2 is the period corresponding to the new prescaler setting.

ATtiny10 数据表(PDF) 19 Page - ATMEL Corporation

ATtiny10 数据表(HTML) 19 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载