 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
ATtiny10 数据表(PDF) 78 Page - ATMEL Corporation |
|
|
|||||||||||||||||||||||||||||
ATtiny10 数据表(HTML) 78 Page - ATMEL Corporation |
|
|
78 / 168 page  78 8127C–AVR–10/09 ATtiny4/5/9/10 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16- bit registers. See “Accessing 16-bit Registers” on page 71. 11.11.7 ICR0H and ICR0L – Input Capture Register 0 The Input Capture is updated with the counter (TCNT0) value each time an event occurs on the ICP0 pin (or optionally on the Analog Comparator output for Timer/Counter0). The Input Capture can be used for defining the counter TOP value. The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit registers. “Accessing 16-bit Registers” on page 71. 11.11.8 TIMSK0 – Timer/Counter Interrupt Mask Register 0 • Bits 7:6, 4:3 – Reserved Bits These bits are reserved for future use. For ensuring compatibility with future devices, these bits must be written to zero when the register is written. • Bit 5 – ICIE0: Timer/Counter0, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter0 Input Capture interrupt is enabled. The corresponding Interrupt Vector (See “Interrupts” on page 66.) is executed when the ICF0 Flag, located in TIFR0, is set. • Bit 2 – OCIE0B: Timer/Counter0, Output Compare B Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter0 Output Compare B Match interrupt is enabled. The corresponding Interrupt Vector (see “Interrupts” on page 35) is executed when the OCF0B flag, located in TIFR0, is set. • Bit 1 – OCIE0A: Timer/Counter0, Output Compare A Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter0 Output Compare A Match interrupt is enabled. The corresponding Interrupt Vector (see “Interrupts” on page 35) is executed when the OCF0A flag, located in TIFR0, is set. • Bit 0 – TOIE0: Timer/Counter0, Overflow Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter0 Overflow interrupt is enabled. The corresponding Interrupt Vector (see “Interrupts” on page 35) is executed when the TOV0 flag, located in TIFR0, is set. Bit 765 432 10 0x23 ICR0[15:8] ICR0H 0x22 ICR0[7:0] ICR0L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 0x2B – –ICIE0 – – OCIE0B OCIE0A TOIE0 TIMSK0 Read/Write R R R/W R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
