CS8427-CSZ datasheet(9/60 Pages) CIRRUS

9 / 60 page

CS8427

DS477F5

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE

Inputs: Logic 0 = 0 V, Logic 1 = VL+; CL = 20 pF.

Notes: 14. If Fso or Fsi is lower than 46.875 kHz, the maximum CCLK frequency should be less than 128 Fso and

less than 128 Fsi. This is dictated by the timing requirements necessary to access the Channel Status

and User Bit buffer memory. Access to the control register file can be carried out at the full 6 MHz rate.

The minimum allowable input sample rate is 8 kHz, so choosing CCLK to be less than or equal to

1.024 MHz should be safe for all possible conditions.

15. Data must be held for sufficient time to bridge the transition time of CCLK.

16. For fsck < 1 MHz.

Parameter

Symbol

Min

Typ

Max

Units

CCLK Clock Frequency

(Note 14)

fsck

6.0

MHz

CS High Time Between Transmissions

tcsh

1.0

μs

CS Falling to CCLK Edge

tcss

CCLK Low Time

tscl

CCLK High Time

tsch

CDIN to CCLK Rising Setup Time

tdsu

CCLK Rising to DATA Hold Time

(Note 15)

tdh

CCLK Falling to CDOUT Stable

tpd

Rise Time of CDOUT

tr1

Fall Time of CDOUT

tf1

Rise Time of CCLK and CDIN

(Note 16)

tr2

100

Fall Time of CCLK and CDIN

(Note 16)

tf2

100

t r2

t f2

t dsu

t dh

t sch

t scl

CCLK

CDIN

t css

t pd

CDOUT

t csh

Figure 3. SPI Mode timing

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