CS8427-CSZ datasheet(18/60 Pages) CIRRUS

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CS8427

DS477F5

7. AES3 TRANSMITTER

The AES3 transmitter encodes and transmits au-

dio and digital data according to the AES3,

IEC60958 (S/PDIF), and EIAJ CP-1201 interface

standards. Audio and control data are multiplexed

together and bi-phase, mark encoded. The result-

ing bit stream is driven to an output connector ei-

ther directly or through a transformer.

The transmitter clock may be derived from the

clock input pin OMCK, or from the incoming data.

If OMCK is asynchronous to the data source, an in-

terrupt bit (TSLIP) is provided that will go high ev-

ery time a data sample is dropped or repeated. Be

aware that the pattern of slips does not have hys-

teresis and so the occurrence of the interrupt con-

dition is not deterministic.

The channel status (C) and user channel (U) bits in

the transmitted data stream are taken from storage

areas within the CS8427. The user can manually

access the internal storage or configure the

CS8427 to run in one of several automatic modes.

The Appendix: Channel Status and User Data

Buffer Management provides detailed descriptions

of each automatic mode and describes methods of

manually accessing the storage areas. The trans-

mitted user data can optionally be input through

the U pin, under the control of a control port regis-

ter bit. Figure 13 shows the timing requirements for

clocking U data through the U pin.

7.1

Transmitted Frame and Channel

Status Boundary Timing

The TCBL pin is used to control or indicate the start

of transmitted channel status block boundaries and

may be used as an input or output.

In some applications, it may be necessary to con-

trol the precise timing of the transmitted AES3

frame boundaries. This may be achieved in three

ways:

1) With TCBL set to input, driving TCBL high for

>3 OMCK clocks will cause a frame start, as well as

a new channel status block start.

2) If the AES3 output comes from the AES3 input, set-

ting TCBL as output will cause AES3 output frame

boundaries to align with AES3 input frame bound-

aries.

3) If the AES3 output comes from the serial audio in-

put port while the port is in slave mode and TCBL

is set to output, the start of the A channel sub-frame

will be aligned with the leading edge of IL-CK.

7.2

TXN and TXP Drivers

The line drivers are low skew, low impedance, dif-

ferential outputs capable of driving cables directly.

Both drivers are set to ground during reset

(RST = low), when no AES3 transmit clock is pro-

vided, and optionally under the control of a register

bit. The CS8427 also allows immediate mute of the

AES3 transmitter audio data through a control reg-

ister bit.

External components are used to terminate and

isolate the external cable from the CS8427. These

components are detailed in Appendix A: External

AES3/SPDIF/IEC60958 Transmitter and Receiver

Components.

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