| 数据搜索系统,热门电子元器件搜索 |
|
CS8427-CSZ 数据表(PDF) 29 Page - Cirrus Logic |
|
|
|||||||||||||||||||||||||||||
CS8427-CSZ 数据表(HTML) 29 Page - Cirrus Logic |
|
29 / 60 page ![]() CS8427 DS477F5 29 MMR - Select AES3 receiver mono or stereo operation Default = ‘0’ 0 - Normal stereo operation 1 - A and B subframes treated as consecutive samples of one channel of data. Data is duplicated to both left and right parallel outputs of the AES receiver block. The input sample rate (Fsi) is doubled compared to MMR=0 MMT - Select AES3 transmitter mono or stereo operation Default = ‘0’ 0 - Normal stereo operation 1 - Output either left or right channel inputs into consecutive subframe outputs (mono mode, left or right is determined by MMTLR bit) MMTCS - Select A or B channel status data to transmit in mono mode Default = ‘0’ 0 - Use channel A CS data for the A subframe and use channel B CS data for the B subframe 1 - Use the same CS data for both the A and B subframe outputs. If MMTLR = 0, use the left channel CS data. If MMTLR = 1, use the right channel CS data. MMTLR - Channel Selection for AES Transmitter mono mode Default = ‘0’ 0 - Use left channel input data for consecutive subframe outputs 1- Use right channel input data for consecutive subframe outputs 11.3 Data Flow Control (03h) The Data Flow Control register configures the flow of audio data to/from the following blocks: Serial Audio Input Port, Serial Audio Output Port, AES3 receiver, and AES3 transmitter. In conjunction with the Clock Source Control regis- ter, multiple Receiver/Transmitter/Transceiver modes may be selected. The output data should be muted prior to changing bits in this register to avoid transients. TXOFF - AES3 Transmitter Output Driver Control Default = ‘0 0 - AES3 transmitter output pin drivers normal operation 1 - AES3 transmitter output pin drivers drive to 0 V. AESBP - AES3 bypass mode selection Default = ‘0’ 0 - Normal operation 1 - Connect the AES3 transmitter driver input directly to the RXP pin, which becomes a normal TTL threshold digital input. The transmitter clock (selecting using the OUTC bit in the Clock Source Control) must be present for the bypass mode to work. TXD1:TXD0 - AES3 Transmitter Data Source Default = ‘01’ 00 - Reserved 01 - Serial audio input port 10 - AES3 receiver 11 - Reserved 7 6 5 4 32 10 0 TXOFF AESBP TXD1 TXD0 SPD1 SPD0 0 |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |