PCF2113DUSLASH2SLASHF4 datasheet(30/65 Pages) NXP

30 / 65 page

PCF2113_FAM_4

Product data sheet

Rev. 04 — 4 March 2008

30 of 65

NXP Semiconductors

PCF2113x

LCD controllers/drivers

Remark: the CGRAM address uses the same address register as the DDRAM address

and consists of 7 bits (A6h to A0h). With the ‘set CGRAM address’ command, only

bits DB5 to DB0 are set. Bit DB6 can be set using the ‘set DDRAM address’ command

ﬁrst, or by using the auto-increment feature during CGRAM write. All bits DB6 to DB0 can

be read using the ‘read busy ﬂag’ and ‘read address’ command.

When writing to the lower part of the CGRAM, ensure that bit DB6 of the address is not

set (e.g. by an earlier DDRAM write or read action).

9.8 Set DDRAM address

‘Set DDRAM address’ writes the DDRAM address ADD into the address counter

(A6h to A0h). Data can then be written to or read from the DDRAM.

9.9 Read busy ﬂag and read address

‘Read busy ﬂag and address counter’ reads the Busy Flag (BF) and Address

Counter (AC). BF = 1 indicates that an internal operation is in progress. The next

instruction will not be executed until BF = 0. It is recommended that the BF status is

checked before the next write operation is executed.

At the same time, the value of the address counter (A6h to A0h) is read out, into DB6 to

DB0. The address counter is used by both CGRAM and DDRAM, and its value is

determined by the previous instruction.

9.10 Write data to CGRAM or DDRAM

‘Write data’ writes binary 8-bit data DB7 to DB0 to the CGRAM or the DDRAM.

Whether the CGRAM or DDRAM is to be written into is determined by the previous ‘set

CGRAM address’ or ‘set DDRAM address’ command. After writing, the address

automatically increments or decrements by 1, in accordance with the entry mode. Only

bits DB4 to DB0 of CGRAM data are valid, bits DB7 to DB5 are ‘not relevant’.

9.11 Read data from CGRAM or DDRAM

‘Read data’ reads binary 8-bit data DB7 to DB0 from the CGRAM or DDRAM.

The most recent ‘set address’ command determines whether the CGRAM or DDRAM is to

be read.

The ‘read data’ instruction gates the content of the Data Register (DR) to the bus while

pin E is HIGH. After pin E goes LOW again, internal operation increments (or decrements)

the AC and stores RAM data corresponding to the new AC into the DR.

There are only three instructions that update the DR:

• ‘Set CGRAM address’

• ‘Set DDRAM address’

• ‘Read data’ from CGRAM or DDRAM

Other instructions (e.g. ‘write data’, ‘cursor/display shift’, ‘clear display’ and ‘return home’)

do not modify the data register content.

PCF2113DU/2/F4 数据表(PDF) 30 Page - NXP Semiconductors

PCF2113DU/2/F4 数据表(HTML) 30 Page - NXP Semiconductors

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