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PCF2113DU/2/F4 数据表(PDF) 44 Page - NXP Semiconductors |
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PCF2113DU/2/F4 数据表(HTML) 44 Page - NXP Semiconductors |
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44 / 65 page ![]() PCF2113_FAM_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 4 March 2008 44 of 65 NXP Semiconductors PCF2113x LCD controllers/drivers [1] Spikes on VDD1 or VSS1 which cause (VDD1 − VSS1) ≤ 1.6 V can cause a Power-on reset. [2] Resets all logic when VDD1 < VPOR; 3 oscillator cycles required. [3] LCD outputs are open-circuit; inputs at VDD1 or VSS1; bus inactive. [4] Tamb =25 °C; fosc = 200 kHz. [5] LCD outputs are open-circuit; VLCD generator is on; load current IDD(LCD) =5 µA (at VLCD). [6] Tested on a sample basis. [7] Resistance of output pins (R1 to R18 and C1 to C60) with a load current of 10 µA; outputs measured one at a time; external V LCD =3V; VDD1 =VDD2 =VDD3 =VLCD. [8] LCD outputs are open-circuit; external VLCD. Pins DB7 to DB0 IOL LOW-level output current VOL = 0.4 V; VDD1 = 5 V 1.6 4 - mA IOH HIGH-level output current VOH = 0.4 V; VDD1 =5V −1 −8- mA Ipu pull-up current VI =VSS1 0.04 0.15 1 µA I2C-bus Input on pins SDA and SCL VI input voltage VSS1 − 0.5 - 5.5 V VIL LOW-level input voltage 0 - 0.3VDD1 V VIH HIGH-level input voltage 0.7VDD1 - 5.5 V ILI input leakage current VI = VDD1 or VSS1 −1- +1 µA CI input capacitance [6] -5 -pF Output on pin SDA IOL(SDA) LOW-level output current on pin SDA VOL = 0.4 V; VDD1 >2V 3 - - mA VOL = 0.2VDD1; VDD1 <2V 2 - - mA LCD outputs RO output resistance row outputs: pins R1 to R18 [7] -10 30 k Ω column outputs: pins C1 to C60 [7] -15 40 k Ω ∆Vbias bias voltage variation pins R1 to R18 and C1 to C60 [8] - 20 130 mV ∆VLCD LCD voltage variation Tamb =25 °C [5] VLCD < 3 V - - 160 mV VLCD < 4 V - - 200 mV VLCD < 5 V - - 260 mV VLCD < 6 V - - 340 mV Table 19. Static characteristics …continued VDD1 = 1.8 V to 5.5 V; VDD2 =VDD3 = 2.2 V to 4.0 V; VSS =0V; VLCD = 2.2 V to 6.5 V; Tamb = −40 °Cto+85 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit |
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