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PCF2113DU/2/F4 数据表(PDF) 6 Page - NXP Semiconductors |
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PCF2113DU/2/F4 数据表(HTML) 6 Page - NXP Semiconductors |
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6 / 65 page ![]() PCF2113_FAM_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 4 March 2008 6 of 65 NXP Semiconductors PCF2113x LCD controllers/drivers [1] Fab 1 identification starts with nnnnnn, where n represents a number between 0 and 9 (8 inch wafer). [2] Fab 2 identification starts with AXnnnn, where X represents a letter or a number and n represents a number between 0 and 9 (6 inch wafer). 811 VLCDIN 92 101 DB7 9 to 16 12 to 19 R9 to R16 93 102 DB6 17 20 R18 94 103 DB5 18 to 25 21 to 28 C60 to C53 95 104 DB4 - 29 dummy pad 96 105 DB3/SA0 - 30 dummy pad 97 106 DB2 26 to 50 31 to 55 C52 to C28 98 107 DB1 - 56 dummy pad 99 108 DB0 - 57 dummy pad 100 109 VDD2 51 to 75 58 to 82 C27 to C3 - 110 VDD3 - 83 dummy pad - - - Table 4. Bonding pad dimensions Pad Size Unit Type galvanic pure Au Bump dimensions (50 ± 6) × (90 ± 6) × (17.5 ± 5) µm Height difference in one die < 2 µm Convex deformation < 5 µm Pad size (aluminium) 62 × 100 µm Passivation opening 36 × 76 µm Pad pitch −635.0 µm Wafer thickness (excluding bumps) 380 ± 25 µm Fab 1 [1] Fab 2 [2] Die size X 3.52 3.47 mm Die size Y 3.36 3.31 mm Table 3. Pin (LQFP100 package) or pad allocation table …continued Pin Pad Symbol Pin Pad Symbol Table 5. Pin and bonding pad description All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip (see Figure 3). Symbol Pin Type Pad X ( µm) Y ( µm) Description VDD1 1P 1 −1345 −1550 supply voltage 1 for all except VLCD generator OSC 2 I 2 −1155 −1550 oscillator and external clock input [1] PD 3 I 3 −1 055 −1550 power-down select input; for normal operation PD is LOW T3 - I 4 −845 −1550 test pad; open circuit and not user accessible T1 4 I 5 −765 −1550 test pin; must be connected to VSS1 T2 - I 6 −665 −1550 test pad; must be connected to VSS1 VSS1 5P 7 −525 −1550 ground 1 for all except VLCD generator |
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