PCF2113DUSLASH2SLASHF4 datasheet(45/65 Pages) NXP

45 / 65 page

PCF2113_FAM_4

Product data sheet

Rev. 04 — 4 March 2008

45 of 65

NXP Semiconductors

PCF2113x

LCD controllers/drivers

15. Dynamic characteristics

Table 20.

Dynamic characteristics

VDD1 = 1.8 V to 5.5 V; VDD2 =VDD3 = 2.2 V to 4.0 V; VSS =0V; VLCD = 2.2 V to 6.5 V; Tamb = −40 °Cto+85 °C;

unless otherwise speciﬁed

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

ffr(LCD)

LCD frame frequency

internal clock; VDD = 5.0 V

147

fosc

oscillator frequency

[1] 140

250

450

kHz

fosc(ext)

external oscillator frequency

140

450

kHz

td(startup)(OSC) start-up delay time on pin OSC

oscillator, after power down

[2] -

200

300

µs

tw(pd)

power-down pulse width

µs

tw(spike)

spike pulse width

on pin PD

[2] -

Timing characteristics of parallel interface [3]

Write operation (writing data from microcontroller to PCF2113x); see Figure 32

tcy(en)

enable cycle time

500

tw(en)

enable pulse width

220

tsu(A)

address set-up time

th(A)

address hold time

tsu(D)

data input set-up time

th(D)

data input hold time

Read operation (reading data from PCF2113x to microcontroller); see Figure 33

tcy(en)

enable cycle time

500

tw(en)

enable pulse width

220

tsu(A)

address set-up time

th(A)

address hold time

td(DV)

data input valid delay time

VDD1 > 2.2 V

150

VDD1 > 1.5 V

250

th(D)

data input hold time

Timing characteristics of I2C-bus interface [3]; see Figure 34

fSCL

SCL frequency

400

tLOW

LOW period of the SCL clock

1.3

µs

tHIGH

HIGH period of the SCL clock

0.6

µs

tSU;DAT

data set-up time

100

tHD;DAT

data hold time

rise time of both SDA and SCL

signals

[2][4] 15 + 0.1Cb

300

fall time of both SDA and SCL

signals

[2][4] 15 + 0.1Cb

300

capacitive load for each bus line

[4] -

400

tSU;STA

set-up time for a repeated

START condition

0.6

µs

tHD;STA

hold time (repeated) START

condition

0.6

µs

PCF2113DU/2/F4 数据表(PDF) 45 Page - NXP Semiconductors

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