68HC05CL48 datasheet(35/145 Pages) MOTOROLA

35 / 145 page

June 11, 1997

GENERAL RELEASE SPECIFICATION

MC68HC05CL48

INTERRUPTS

MOTOROLA

REV 2.0

4-3

4.1

RESET INTERRUPT SEQUENCE

The RESET function is not in the strictest sense an interrupt; however, it is acted

upon in a similar manner as shown in Figure 4-1. A low level input on the RESET

pin or internal generated reset signal causes the program to vector to its starting

address which is speciﬁed by the contents of memory locations $FFFE and

$FFFF. The I-bit in the condition code register is also set. The MCU is conﬁgured

to a known state during this type of reset as described in Section 5.

4.2

SOFTWARE INTERRUPT (SWI)

The SWI is an executable instruction and a non-maskable interrupt since it is

executed regardless of the state of the I-bit in the CCR. If the I-bit is zero

(interrupts enabled), the SWI instruction executes after interrupts which were

pending before the SWI was fetched, or before interrupts if interrupts were

generated after the SWI was fetched. The interrupt service routine address is

speciﬁed by the contents of memory locations $FFFC and $FFFD.

4.3

HARDWARE INTERRUPTS

All hardware interrupts except RESET are maskable by the I-bit in the CCR. If the

I-bit is set, all hardware interrupts (internal and external) are disabled. Clearing

the I-bit enables the hardware interrupts. There are six types of hardware

interrupts which are explained in the following sections.

4.3.1 External Interrupt (IRQ)

If the IRQ option is both level and edge sensitive triggering (INTO=0), a low level

or an negative edge at the IRQ pin and the interrupt mask bit of the condition code

ﬁnished with the interrupt service routine, but the IRQ pin is still low, the

EXTERNAL Interrupt will start again. In fact, the MCU will keep on servicing the

EXTERNAL Interrupt as long as the IRQ pin is low. If the IRQ pin goes low for a

while and resumes to high (a negative pulse) before the interrupt mask bit is

cleared, the MCU will not recognize there was an interrupt request, and no

interrupt will occur after the interrupt mask bit is cleared, i.e. there is no latch for

the interrupt signal for the level sensitive triggering.

If the IRQ option is negative edge sensitive triggering (INTO=1), a negative edge

occurs at the IRQ pin and the interrupt mask bit of the condition code register is

cleared will cause an EXTERNAL Interrupt to occur. If the MCU has ﬁnished with

the interrupt service routine, but the IRQ pin has not resumed back to high, no

further interrupt will be generated. The interrupt logic recognizes negative edge

transitions and pulses (special case of negative edges) only. If the negative edge

occurs during the interrupt mask bit is set, the interrupt signal will be latched, an

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