68HC05CL48 datasheet(76/145 Pages) MOTOROLA

76 / 145 page

GENERAL RELEASE SPECIFICATION

June 11, 1997

MOTOROLA

SERIAL PERIPHERAL INTERFACE

MC68HC05CL48

9-4

REV 2.0

9.2.1 SPCR SPI Control Register

SPIE SPI Interrupt Enable

When this bit is set to a one a hardware interrupt sequence is requested each

time the SPIF or MODF status ﬂag is set. SPI interrupts are inhibited if this bit is

clear or if the I-bit in the CC-Register is one.

SPE

SPI System Enable

Setting the SPE-bit to ‘1’ will enable the SPI function and automatically

conﬁgure PTC[3:0] as dedicated SPI pins.

MSTR Master/Slave Mode Select

0 =

Slave mode

1 =

Master mode

CPOL Clock Polarity

CPHA Clock Phase

These two bits are used to specify the clock format to be used in SPI

operations. Please refer to Figure 9-1.

SPR1, SPR0 SPI Clock (SCK) Rate Select Bits

These bits are used to specify the SPI clock rate.

76543210

SPCR

$0020

READ

SPIE

SPE

MSTR

CPOL

CPHA

SPR1

SPR0

WRITE

RESET

001

Table 9-1. SPI Clock Rates

SPR1

SPR0

E Clock

divided-by

Frequency

Eclk = 1.8 MHz (baud

rate)

0.9 MHz

450 kHz

112.5 kHz

56.25 kHz

68HC05CL48 数据表(PDF) 76 Page - Motorola, Inc

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