68HC05CL48 datasheet(83/145 Pages) MOTOROLA

83 / 145 page

June 6, 1997

GENERAL RELEASE SPECIFICATION

MC68HC05CL48

ANALOG TO DIGITAL CONVERTER

MOTOROLA

REV 2.0

10-3

10.4.3 ADON - A/D On

When the A/D is turned on (ADON = 1), it requires a time t

ADON for the current sources to

stabilize, and results can be inaccurate during this time. This bit turns on the charge pump.

If the ADRC is set, clearing this bit disables the RC oscillator to save power.

10.4.4 CH2:CH0 - Channel Select Bits

CH2, CH1, and CH0 form a 3-bit field which is used to select one of eight A/D channels.

Channels 0-3 correspond to the analog input pins: ATD(3:0) in the MCU. Channels 4-7

are used for internal reference points. The following table shows the signals selected by

the channel select field.

10.5

A/D DATA REGISTER (ADDR)

One 8-bit result register is provided. This register is updated each time COCO is set

10.6

A/D DURING WAIT MODE

The A/D continues normal operation during WAIT mode. To decrease power consumption

during WAIT, it is recommended that both the ADON and ADRC bits in the A/D Status and

Control Register be cleared if the A/D converter is not being used. If the A/D converter is

in use and the system clock rate is above 1.0 MHz, it is recommended that the ADRC bit

be cleared.

CHANNEL

SIGNAL

ATD0 pin

ATD1 pin

ATD2/PTC[4] pin

ATD3/PTC[5] pin

4VRH

5VRL

6(VRH - VRL)/4

7(VRH - VRL)/2

Table 10-1. A/D Channel Assignments

76543210

ADDR

$0025

READ

ADDR7

ADDR6

ADDR5

ADDR4

ADDR3

ADDR2

ADDR1

ADDR0

WRITE

RESET

UUUUUUUU

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