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68HC05CL48 数据表(PDF) 44 Page - Motorola, Inc |
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68HC05CL48 数据表(HTML) 44 Page - Motorola, Inc |
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44 / 145 page  GENERAL RELEASE SPECIFICATION June 11, 1997 MOTOROLA RESETS MC68HC05CL48 5-2 REV 2.0 5.3 COMPUTER OPERATING PROPERLY RESET (COPR) The internal COPR reset is generated automatically (if enabled) by a time-out of the COP Watchdog Timer. This time-out occurs if the counter in the COP Watchdog Timer is not reset (cleared) within a specific time by a program reset sequence. The COP Watchdog Timer can be enabled by setting bit 6 of the Option Register at $001F. Refer to Section 8 for more information on this time-out feature. The COP Watchdog reset will activate the internal pulldown device connected to the RESET pin for one cycle of the internal clock, PH2. The COP register shares the same address ($FFF0) with the MS byte of the Core Timer Interrupt Vector as shown below. Reading this location will return the MS byte of the Core Timer Interrupt Vector. Writing $00 to this location clears the COP watchdog timer. 76543210 COPR $FFF0 READ WRITE COPR POR UUUUUUU 0 U = UNAFFECTED |
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