68HC05CL48 datasheet(9/145 Pages) MOTOROLA

9 / 145 page

June 11, 1997

GENERAL RELEASE SPECIFICATION

MC68HC05CL48

MOTOROLA

REV 2.0

vii

LIST OF FIGURES

Figure

Title

Page

1-1

MC68HC05CL48 Block Diagram ..................................................................... 1-3

1-2

MC68HC05CL48 Pin Assignments .................................................................. 1-4

1-3

Power Supply Decoupling ................................................................................ 1-5

1-4

Oscillator Connections ..................................................................................... 1-7

2-1

MC68HC05CL48 Memory Map........................................................................ 2-3

2-2

MC68HC05CL48 I/O Registers $0000-$000F ................................................. 2-4

2-3

MC68HC05CL48 I/O Registers $0010-$001F ................................................. 2-5

2-4

MC68HC05CL48 I/O Registers $0020-$002F ................................................. 2-6

3-1

MC68HC05 Programming Model ..................................................................... 3-1

4-1

Interrupt Processing Flowchart ........................................................................ 4-2

4-2

External Interrupts............................................................................................ 4-5

4-3

Keyboard Interrupt Circuitry ............................................................................. 4-7

6-1

STOP/WAIT Flowchart..................................................................................... 6-3

7-1

Port I/O Circuitry............................................................................................... 7-1

8-1

16-Bit Free-running Timer Block Diagram........................................................ 8-2

8-2

Timer State Diagram For Timer Overflow ........................................................ 8-4

8-3

Timer State Timing Diagram For Reset ........................................................... 8-5

8-4

Timer State Timing Diagram For Output Compare .......................................... 8-8

8-5

Timer State Timing Diagram For Input Capture ............................................. 8-11

8-6

Core Timer Block Diagram............................................................................. 8-15

8-7

ONE Second Watch Timer............................................................................. 8-20

9-1

SPI Clock/Data Relationships .......................................................................... 9-5

11-1

Caller ID Block Diagram................................................................................. 11-1

11-2

Carrier Detect Interface.................................................................................. 11-2

11-3

RT_L Interrupt ................................................................................................ 11-3

11-4

Ring Detect Interface ..................................................................................... 11-3

11-5

Power Up Sequence from STOP Mode ......................................................... 11-4

11-6

Power Up Sequence from WAIT Mode .......................................................... 11-5

11-7

8-bit Caller ID Data Timing Diagram .............................................................. 11-6

11-8

Single Message Format ............................................................................... 11-11

11-9

CLID Timing Diagram................................................................................... 11-11

12-1

LCD Driver Block Diagram ............................................................................. 12-1

12-2

LCD 5:1 bias waveforms ................................................................................ 12-5

12-3

LCD 4:1 bias waveforms ................................................................................ 12-6

12-4

Voltage Generator.......................................................................................... 12-7

13-1

Phase Lock Loop Block Diagram ................................................................... 13-3

13-2

Typical Waveform for PLL.............................................................................. 13-3

16-1

112-Pin TQFP Mechanical Dimensions ......................................................... 16-2

16-2

100-Pin TQFP Mechanical Dimensions ......................................................... 16-3

A-1

MC68HC705CL48 Memory Map......................................................................A-2

A-2

EPROM Programming Sequence ....................................................................A-4

B-1

MC68HC05CL16 Block Diagram .....................................................................B-2

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