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68HC05CL48 数据表(PDF) 79 Page - Motorola, Inc |
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68HC05CL48 数据表(HTML) 79 Page - Motorola, Inc |
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79 / 145 page  June 11, 1997 GENERAL RELEASE SPECIFICATION MC68HC05CL48 SERIAL PERIPHERAL INTERFACE MOTOROLA REV 2.0 9-7 exchanged between the master and the slave. Note that some slave devices are very simple and either accept data from the master without returning data to the master or pass data to the master without requiring data from the master. When writing the SPDR, the data is written directly into the shift register and always shifted out MSB first. When reading the SPDR, a Read Data Buffer is actually accessed. This buffer contains the last data byte received by the SPI, and is updated during the cycle that SPIF is set (reception complete). |
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