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MPC8572ECVTATLD 数据表(PDF) 107 Page - Freescale Semiconductor, Inc |
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MPC8572ECVTATLD 数据表(HTML) 107 Page - Freescale Semiconductor, Inc |
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107 / 140 page  MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 107 Package Description TSEC1_TX_EN/FIFO1_TX_EN /FIFO1_TXC[0] Transmit Enable AJ24 O LVDD 1, 22 TSEC1_TX_ER/FIFO1_TX_ER R/FIFO1_TXC[1] Transmit Error AK25 O LVDD 1, 5, 9 Three-Speed Ethernet Controller 2 TSEC2_RXD[7:0]/FIFO2_RXD[ 7:0]/FIFO1_RXD[15:8] Receive Data AG22, AH20, AL22, AG20, AK21, AK22, AJ21, AK20 ILVDD 1 TSEC2_TXD[7:0]/FIFO2_TXD[ 7:0]/FIFO1_TXD[15:8] Transmit Data AH21, AF20, AC17, AF21, AD18, AF22, AE20, AB18 OLVDD 1, 5, 9, 24 TSEC2_COL/FIFO2_TX_FC Collision Detect/Flow Control AE19 I LVDD 1 TSEC2_CRS/FIFO2_RX_FC Carrier Sense/Flow Control AJ20 I/O LVDD 1, 16 TSEC2_GTX_CLK Transmit Clock Out AE18 O LVDD — TSEC2_RX_CLK/FIFO2_RX_C LK Receive Clock AL23 I LVDD 1 TSEC2_RX_DV/FIFO2_RX_DV /FIFO1_RXC[2] Receive Data Valid AJ22 I LVDD 1 TSEC2_RX_ER/FIFO2_RX_E R Receive Data Error AD19 I LVDD 1 TSEC2_TX_CLK/FIFO2_TX_C LK Transmit Clock In AC19 I LVDD 1 TSEC2_TX_EN/FIFO2_TX_EN /FIFO1_TXC[2] Transmit Enable AB19 O LVDD 1, 22 TSEC2_TX_ER/FIFO2_TX_ER R Transmit Error AB17 O LVDD 1, 5, 9 Three-Speed Ethernet Controller 3 TSEC3_TXD[3:0]/FEC_TXD[3: 0]/FIFO3_TXD[3:0] Transmit Data AG18, AG17, AH17, AH19 OTVDD 1, 5, 9 TSEC3_RXD[3:0]/FEC_RXD[3: 0]/FIFO3_RXD[3:0] Receive Data AG16, AK19, AD16, AJ19 ITVDD 1 TSEC3_GTX_CLK Transmit Clock Out AE17 O TVDD TSEC3_RX_CLK/FEC_RX_CL K/FIFO3_RX_CLK Receive Clock AF17 I TVDD 1 TSEC3_RX_DV/FEC_RX_DV/F IFO3_RX_DV Receive Data Valid AG14 I TVDD 1 TSEC3_RX_ER/FEC_RX_ER/ FIFO3_RX_ER Receive Error AH15 I TVDD 1 Table 75. MPC8572E Pinout Listing (continued) Signal Signal Name Package Pin Number Pin Type Power Supply Notes |
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