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MPC8572ECVTATLD 数据表(PDF) 108 Page - Freescale Semiconductor, Inc |
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MPC8572ECVTATLD 数据表(HTML) 108 Page - Freescale Semiconductor, Inc |
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108 / 140 page  MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 108 Freescale Semiconductor Package Description TSEC3_TX_CLK/FEC_TX_CL K/FIFO3_TX_CLK Transmit Clock In AF16 I TVDD 1 TSEC3_TX_EN/FEC_TX_EN/F IFO3_TX_EN Transmit Enable AJ18 O TVDD 1, 22 Three-Speed Ethernet Controller 4 TSEC4_TXD[3:0]/TSEC3_TXD[ 7:4]/FIFO3_TXD[7:4] Transmit Data AD15, AC16, AC14, AB16 OTVDD 1, 5, 9 TSEC4_RXD[3:0]/TSEC3_RXD [7:4]/FIFO3_RXD[7:4] Receive Data AE15, AF13, AE14, AH14 ITVDD 1 TSEC4_GTX_CLK Transmit Clock Out AB14 O TVDD — TSEC4_RX_CLK/TSEC3_COL/ FEC_COL/FIFO3_TX_FC Receive Clock AG13 I TVDD 1 TSEC4_RX_DV/TSEC3_CRS/ FEC_CRS/FIFO3_RX_FC Receive Data Valid AD13 I/O TVDD 1, 23 TSEC4_TX_EN/TSEC3_TX_E R/FEC_TX_ER/FIFO3_TX_ER Transmit Enable AB15 O TVDD 1, 22 DUART UART_CTS[0:1] Clear to Send W30, Y27 I OVDD — UART_RTS[0:1] Ready to Send W31, Y30 O OVDD 5, 9 UART_SIN[0:1] Receive Data Y26, W29 I OVDD — UART_SOUT[0:1] Transmit Data Y25, W26 O OVDD 5, 9 I2C Interface IIC1_SCL Serial Clock AC30 I/O OVDD 4, 20 IIC1_SDA Serial Data AB30 I/O OVDD 4, 20 IIC2_SCL Serial Clock AD30 I/O OVDD 4, 20 IIC2_SDA Serial Data AD29 I/O OVDD 4, 20 SerDes (x10) PCIe, SRIO SD1_RX[7:0] Receive Data (positive) P32, N30, M32, L30, G30, F32, E30, D32 IXVDD_SR DS1 — SD1_RX[7:0] Receive Data (negative) P31, N29, M31, L29, G29, F31, E29, D31 IXVDD_SR DS1 — SD1_TX[7] PCIe1 Tx Data Lane 7 / SRIO or PCIe2 Tx Data Lane 3 / PCIe3 TX Data Lane 1 M26 O XVDD_SR DS1 — Table 75. MPC8572E Pinout Listing (continued) Signal Signal Name Package Pin Number Pin Type Power Supply Notes |
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