Operation

M48T201Y, M48T201V

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2

Operation

is automatically adjusted for months with less than 31 days and corrects for leap years (valid

until 2100). The internal watchdog timer provides programmable alarm windows.

The nine clock bytes (7FFFFh-7FFF9h and 7FFF1h) are not the actual clock counters, they

are memory locations consisting of BiPORT™ READ/WRITE memory cells within the static

RAM array. Clock circuitry updates the clock bytes with current information once per second.

The information can be accessed by the user in the same manner as any other location in

the static memory array. Byte 7FFF8h is the clock control register. This byte controls user

access to the clock information and also stores the clock calibration setting.

Byte 7FFF7h contains the watchdog timer setting. The watchdog timer can generate either a

reset or an interrupt, depending on the state of the watchdog steering bit (WDS). Bytes

7FFF6h-7FFF2h include bits that, when programmed, provide for clock alarm functionality.

Alarms are activated when the register content matches the month, date, hours, minutes,

and seconds of the clock registers. Byte 7FFF1h contains century information. Byte 7FFF0h

contains additional flag information pertaining to the watchdog timer, the alarm condition,

the battery status and square wave output operation. 4 bits are included within this register

(RS0-RS3) that are used to program the square wave output frequency (see Table 7 on

page 21). The M48T201Y/V also has its own power-fail detect circuit. This control circuitry

the battery, maintaining data and clock operation until valid power is restored.

2.1

Address decoding

The M48T201Y/V accommodates 19 address lines (A0-A18) which allow direct connection

of up to 512 K bytes of static RAM. Regardless of SRAM density used, timekeeping,

watchdog, alarm, century, flag, and control registers are located in the upper RAM locations.

All TIMEKEEPER registers reside in the upper RAM locations without conflict by inhibiting

are transparent to the user and the memory map looks continuous from the first clock

address to the upper most attached RAM addresses.