M48T201Y, M48T201V

Clock operation

21/37

In order to perform a software reset of the watchdog timer, the original timeout period can be

written into the watchdog register, effectively restarting the countdown cycle.

Should the watchdog timer time out, and the WDS bit is programmed to output an interrupt,

a value of 00h needs to be written to the watchdog register in order to clear the IRQ/FT pin.

This will also disable the watchdog function until it is again programmed correctly. A READ

of the flags register will reset the watchdog flag (bit D7; register 7FFF0h).

The watchdog function is automatically disabled upon power-down and the watchdog

register is cleared. If the watchdog function is set to output to the IRQ/FT pin and the

frequency test function is activated, the watchdog or alarm function prevails and the

frequency test function is denied.

Note:

The user must transition the address (or toggle chip enable) to see the flag bit change.

3.7

Square wave output

The M48T201Y/V offers the user a programmable square wave function which is output on

the SQW pin. RS3-RS0 bits located in 7FFF0h establish the square wave output frequency.

These frequencies are listed in Table 7. Once the selection of the SQW frequency has been

completed, the SQW pin can be turned on and off under software control with the square

wave enable bit (SQWE) located in register 7FFF6h.

Table 7.

Square wave output frequency

Square wave bits

Square wave

RS3RS2

RS1RS0

Frequency

Units

000

0

Hi-Z

-

0

0

0

1

32.768

kHz

001

0

8.192

kHz

001

1

4.096

kHz

010

0

2.048

kHz

010

1

1.024

kHz

011

0

512

Hz

011

1

256

Hz

100

0

128

Hz

100

1

64

Hz

101

0

32

Hz

101

1

16

Hz

110

0

8

Hz

110

1

4

Hz

111

0

2

Hz

111

1

1

Hz